Alternatives and similar repositories for safety_island

Users that are interested in safety_island are comparing it to the libraries listed below

• pulp-platform / axi_llc
  ☆33Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆33Updated last year
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆31Updated 7 years ago
• pulp-platform / ace
  ☆20Updated 3 weeks ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated 2 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆23Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated this week
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆18Updated last year
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• pulp-platform / apb
  APB Logic
  ☆22Updated last month
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 2 months ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆33Updated last month
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• AbdelrahmanYassien11 / Verification-of-an-Asynchronous-FIFO-using-UVM-SVA
  Verification of an Asynchronous FIFO using UVM & SVA
  ☆11Updated 6 months ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆27Updated 6 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆33Updated 3 weeks ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆18Updated 10 months ago