mathis-s / SoomRVLinks
A simple superscalar out-of-order RISC-V microprocessor
☆207Updated 4 months ago
Alternatives and similar repositories for SoomRV
Users that are interested in SoomRV are comparing it to the libraries listed below
Sorting:
- Simple 3-stage pipeline RISC-V processor☆139Updated last year
- Ariane is a 6-stage RISC-V CPU☆140Updated 5 years ago
- Unit tests generator for RVV 1.0☆88Updated 2 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆154Updated 3 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 7 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆201Updated 2 weeks ago
- ☆37Updated 2 years ago
- ☆292Updated last week
- Modeling Architectural Platform☆194Updated this week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆167Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆271Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆260Updated 2 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆397Updated this week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆180Updated last week
- A simple RISC V core for teaching☆192Updated 3 years ago
- ☆181Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- CORE-V Family of RISC-V Cores☆278Updated 5 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 4 years ago
- Instruction Set Generator initially contributed by Futurewei☆289Updated last year
- RISC-V microcontroller IP core developed in Verilog☆174Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆214Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- ☆12Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆240Updated 8 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆69Updated 2 weeks ago
- 伴伴學 RISC-V RV32I Architecture CPU☆30Updated 2 years ago
- RISC-V Verification Interface☆97Updated last month
- Self checking RISC-V directed tests☆110Updated last month
- RISC-V Torture Test☆196Updated last year