A simple superscalar out-of-order RISC-V microprocessor
☆254Feb 24, 2025Updated last year
Alternatives and similar repositories for SoomRV
Users that are interested in SoomRV are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,196Aug 18, 2026Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- Simple 3-stage pipeline RISC-V processor☆150Feb 24, 2026Updated 6 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆191Apr 4, 2026Updated 4 months ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Fast, Low-Overhead On-chip Network☆336Updated this week
- Browser-based instruction pipeline visualizer for Onikiri2-Kanata and gem5 O3PipeView traces. Run it online or download a self-contained …☆566Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆236Aug 25, 2020Updated 6 years ago
- A minimalist RISC-V system emulator capable of running Linux kernel with efficient event-driven scheduling☆309Aug 9, 2026Updated 3 weeks ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- ☆325Jan 23, 2026Updated 7 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆76May 15, 2023Updated 3 years ago
- Compact and Efficient RISC-V RV32I[MAFC] emulator☆576Aug 9, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆36Updated this week
- VRoom! RISC-V CPU☆522Sep 2, 2024Updated 2 years ago
- RISC-V Zve32x Vector Coprocessor☆221Jan 22, 2026Updated 7 months ago
- VeeR EH2 core☆276Jul 20, 2026Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- Effective System Call Aggregation☆39Nov 3, 2022Updated 3 years ago
- Chisel RISC-V Vector 1.0 Implementation☆157Updated this week
- The official NaplesPU hardware code repository☆36Jul 27, 2019Updated 7 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆383Jul 12, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- GEMM and GEMM-Ops accelerator for PULP systems☆115Aug 5, 2026Updated 3 weeks ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆43Updated this week
- Bootstrapping a C compiler from scratch☆16Jul 3, 2023Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,297Sep 18, 2021Updated 4 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 6 years ago
- ☆164Jun 8, 2026Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆247Updated this week
- A red-black tree implementation☆44Oct 15, 2025Updated 10 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Mar 27, 2018Updated 8 years ago
- A simple serial console utility☆18May 4, 2026Updated 3 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆365Updated this week
- A minimalist type 2 hypervisor using Linux Kernel Virtual Machine (KVM)☆204Apr 30, 2026Updated 4 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,228Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆113Aug 19, 2026Updated 2 weeks ago
- HW Design Collateral for Caliptra RoT IP☆151Updated this week