A simple superscalar out-of-order RISC-V microprocessor
☆239Feb 24, 2025Updated last year
Alternatives and similar repositories for SoomRV
Users that are interested in SoomRV are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,152Feb 21, 2026Updated last week
- Simple 3-stage pipeline RISC-V processor☆146Feb 24, 2026Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184May 8, 2025Updated 9 months ago
- A Fast, Low-Overhead On-chip Network☆269Updated this week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆34Updated this week
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- A minimalist RISC-V system emulator capable of running Linux kernel with efficient event-driven scheduling☆289Jan 3, 2026Updated 2 months ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆521Apr 8, 2024Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆226Aug 25, 2020Updated 5 years ago
- Compact and Efficient RISC-V RV32I[MAFC] emulator☆539Feb 9, 2026Updated 3 weeks ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- ☆309Jan 23, 2026Updated last month
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- ☆34Feb 17, 2026Updated 2 weeks ago
- Bootstrapping a C compiler from scratch☆13Jul 3, 2023Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37May 4, 2024Updated last year
- VRoom! RISC-V CPU☆518Sep 2, 2024Updated last year
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆320Feb 24, 2026Updated last week
- RISC-V Zve32x Vector Coprocessor☆207Jan 22, 2026Updated last month
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 4 years ago
- ☆132Aug 14, 2025Updated 6 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 5 years ago
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 3 weeks ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- A red-black tree implementation☆42Oct 15, 2025Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- ☆258Dec 22, 2022Updated 3 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- ☆93Feb 24, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆138Updated this week
- Effective System Call Aggregation☆39Nov 3, 2022Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆34Jun 30, 2021Updated 4 years ago
- ☆18May 13, 2025Updated 9 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week