mathis-s / SoomRVLinks
A simple superscalar out-of-order RISC-V microprocessor
☆237Updated 10 months ago
Alternatives and similar repositories for SoomRV
Users that are interested in SoomRV are comparing it to the libraries listed below
Sorting:
- Simple 3-stage pipeline RISC-V processor☆143Updated last week
- ☆44Updated 2 years ago
- ☆304Updated 2 months ago
- Ariane is a 6-stage RISC-V CPU☆152Updated 6 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆198Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- A simple RISC V core for teaching☆198Updated 4 years ago
- ☆192Updated 2 years ago
- Unit tests generator for RVV 1.0☆99Updated 2 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆289Updated last month
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆283Updated last week
- Modeling Architectural Platform☆215Updated last week
- RISC-V IOMMU Specification☆146Updated this week
- RISC-V Torture Test☆208Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆252Updated last year
- Instruction Set Generator initially contributed by Futurewei☆304Updated 2 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆461Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆315Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆483Updated last month
- ☆101Updated 4 months ago
- Open-source RISC-V microcontroller for embedded and FPGA applications☆189Updated last week
- PLIC Specification☆150Updated 4 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- RISC-V Virtual Prototype☆183Updated last year
- RISC-V SystemC-TLM simulator☆335Updated 2 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆234Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆135Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Updated last week
- ☆636Updated last week