mathis-s / SoomRVLinks
A simple superscalar out-of-order RISC-V microprocessor
☆213Updated 6 months ago
Alternatives and similar repositories for SoomRV
Users that are interested in SoomRV are comparing it to the libraries listed below
Sorting:
- Simple 3-stage pipeline RISC-V processor☆140Updated this week
- ☆294Updated 2 weeks ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆185Updated last week
- Unit tests generator for RVV 1.0☆89Updated 2 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- ☆38Updated 2 years ago
- Ariane is a 6-stage RISC-V CPU☆142Updated 5 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆278Updated last week
- Instruction Set Generator initially contributed by Futurewei☆293Updated last year
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 9 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- RISC-V Torture Test☆197Updated last year
- ☆182Updated last year
- RISC-V IOMMU Specification☆128Updated last week
- Modeling Architectural Platform☆201Updated this week
- CORE-V Family of RISC-V Cores☆289Updated 6 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆303Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated last week
- Vector Acceleration IP core for RISC-V*☆183Updated 3 months ago
- 伴伴學 RISC-V RV32I Architecture CPU☆30Updated 2 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆275Updated this week
- PLIC Specification☆145Updated 3 weeks ago
- RISC-V microcontroller IP core developed in Verilog☆178Updated 4 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- ☆587Updated this week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆210Updated 3 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆404Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 3 months ago