mathis-s / SoomRV

Related projects: ⓘ

• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆131Updated 3 months ago
• eisl-nctu / aquila
  Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.
  ☆23Updated 10 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆112Updated 4 years ago
• yutongshen / RISC-V_SoC
  ☆24Updated last year
• riscv / riscv-CMOs
  ☆76Updated 2 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆237Updated last week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆130Updated 3 weeks ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆84Updated last week
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆263Updated this week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆237Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆154Updated 9 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆156Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆213Updated last month
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆143Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆210Updated last week
• yutongshen / RISC-V-Simulator
  ☆23Updated last year
• riscv / riscv-plic-spec
  PLIC Specification
  ☆130Updated last year
• ninolomata / bao-cva6-guide
  ☆9Updated 10 months ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆142Updated last week
• riscv / riscv-aclint
  ☆39Updated 2 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆179Updated this week
• SpinalHDL / NaxRiscv
  ☆257Updated 3 weeks ago
• riscvarchive / riscv-code-size-reduction
  ☆150Updated 6 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆255Updated 11 months ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆22Updated last year
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆91Updated 5 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆208Updated last month
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆138Updated 10 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆126Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆148Updated 4 years ago