mathis-s / SoomRVLinks
A simple superscalar out-of-order RISC-V microprocessor
☆206Updated 3 months ago
Alternatives and similar repositories for SoomRV
Users that are interested in SoomRV are comparing it to the libraries listed below
Sorting:
- Simple 3-stage pipeline RISC-V processor☆140Updated last year
- ☆287Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆282Updated last year
- Ariane is a 6-stage RISC-V CPU☆137Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆257Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 6 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆268Updated this week
- RISC-V Torture Test☆195Updated 10 months ago
- A simple RISC V core for teaching☆188Updated 3 years ago
- ☆175Updated last year
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆213Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆237Updated 6 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆259Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆497Updated 3 months ago
- CORE-V Family of RISC-V Cores☆269Updated 3 months ago
- Unit tests generator for RVV 1.0☆85Updated 2 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆158Updated this week
- RISC-V microcontroller IP core developed in Verilog☆173Updated last month
- RISC-V IOMMU Specification☆117Updated 3 weeks ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆214Updated last week
- ☆564Updated 3 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆380Updated this week
- RISC-V Verification Interface☆92Updated 3 months ago
- Modeling Architectural Platform☆189Updated this week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆151Updated last week
- RISC-V Virtual Prototype☆169Updated 5 months ago
- VeeR EL2 Core☆278Updated last week
- 64-bit multicore Linux-capable RISC-V processor☆93Updated last month
- RISC-V Processor Trace Specification☆182Updated 2 weeks ago