zero-day-labs / riscv-iommu

Related projects: ⓘ

• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆84Updated last week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆26Updated 4 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆85Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆84Updated 3 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆61Updated 2 months ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆26Updated 2 weeks ago
• riscv / riscv-CMOs
  ☆76Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆115Updated this week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆59Updated 2 months ago
• sifive / block-inclusivecache-sifive
  ☆71Updated 2 years ago
• riscv / riscv-aclint
  ☆39Updated 2 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆76Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆48Updated 3 weeks ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆95Updated 4 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆50Updated 11 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆33Updated this week
• chipsalliance / tilelink
  ☆23Updated 7 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆63Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆57Updated 5 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆102Updated 2 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 3 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆67Updated 3 weeks ago
• riscv / riscv-aia
  ☆72Updated 3 weeks ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆105Updated last year
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆54Updated 7 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆161Updated last month
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆74Updated last week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆86Updated 3 years ago
• ucb-bar / sha3
  ☆76Updated 6 months ago