Alternatives and similar repositories for riscv-iommu

Users that are interested in riscv-iommu are comparing it to the libraries listed below

• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆46Updated 11 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 4 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆145Updated last week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆72Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆76Updated last month
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆190Updated 3 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• chipsalliance / tilelink
  ☆38Updated last year
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆43Updated last month
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆124Updated last week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated 2 years ago
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆37Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆99Updated 2 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆56Updated 4 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆72Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆206Updated last year
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆43Updated last year
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆51Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆126Updated 3 months ago