Aquaticfuller / OpenExSys_CoherentCacheLinks
OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
☆15Updated 6 months ago
Alternatives and similar repositories for OpenExSys_CoherentCache
Users that are interested in OpenExSys_CoherentCache are comparing it to the libraries listed below
Sorting:
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆20Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
- commit rtl and build cosim env☆15Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 8 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- ☆29Updated 5 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆26Updated 7 months ago
- ☆17Updated 10 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆27Updated last year
- ☆10Updated 3 years ago
- ☆26Updated 4 years ago
- ☆36Updated 6 years ago
- ☆12Updated 9 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- ☆29Updated last month
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- AXI Interconnect☆52Updated 4 years ago