OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
☆25Mar 25, 2025Updated last year
Alternatives and similar repositories for OpenExSys_CoherentCache
Users that are interested in OpenExSys_CoherentCache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆20Updated this week
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆39Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated 2 years ago
- ☆26Jul 22, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Simple AMBA VIP, Include axi/ahb/apb☆36Jul 4, 2024Updated 2 years ago
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- ☆48Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆197Nov 18, 2024Updated last year
- 自建 chisel 工程模板☆15Jul 19, 2023Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- The official NaplesPU hardware code repository☆36Jul 27, 2019Updated 7 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 3 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆45Aug 10, 2022Updated 4 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆28Jan 6, 2026Updated 7 months ago
- FIR filter implementation☆29Mar 19, 2020Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆336Aug 14, 2026Updated 2 weeks ago
- A reliable, real-time subsystem for the Carfield SoC☆21Dec 2, 2025Updated 8 months ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated last year
- ☆61Aug 30, 2021Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- ☆15Jul 12, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Sep 17, 2023Updated 2 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- ☆25Apr 18, 2021Updated 5 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆37Mar 13, 2025Updated last year
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- ☆11Nov 8, 2017Updated 8 years ago
- 通用的测试平台日志，波形(FSDB/VCD)，根因分析MCP Server. A Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Waveform Analys…☆86Updated this week
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- ☆33Jan 7, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆17Mar 8, 2026Updated 5 months ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Nov 27, 2025Updated 9 months ago
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 5 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago