phanrahan / magmaLinks
magma circuits
☆262Updated last year
Alternatives and similar repositories for magma
Users that are interested in magma are comparing it to the libraries listed below
Sorting:
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆235Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆299Updated 2 weeks ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆431Updated 2 months ago
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆289Updated 3 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆422Updated last month
- SystemVerilog synthesis tool☆215Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆269Updated last month
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆218Updated last week
- SystemRDL 2.0 language compiler front-end☆261Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆345Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆226Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆269Updated last week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆284Updated 3 weeks ago
- Build Customized FPGA Implementations for Vivado☆341Updated this week
- Python-based hardware modeling framework☆244Updated 6 years ago
- SystemVerilog frontend for Yosys☆166Updated last week
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- PandA-bambu public repository☆290Updated 3 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆127Updated last month
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆288Updated 2 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆475Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated this week
- ☆104Updated 3 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆613Updated this week
- Next generation CGRA generator☆115Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆306Updated 3 months ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated last month
- Python wrapper for verilator model☆91Updated last year
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆133Updated 6 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆534Updated last week