phanrahan / magmaLinks
magma circuits
☆262Updated 11 months ago
Alternatives and similar repositories for magma
Users that are interested in magma are comparing it to the libraries listed below
Sorting:
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆290Updated 2 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆431Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆294Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆233Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆266Updated last week
- SystemVerilog synthesis tool☆211Updated 6 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆344Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆416Updated last month
- Python-based hardware modeling framework☆244Updated 5 years ago
- Build Customized FPGA Implementations for Vivado☆343Updated this week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆217Updated 3 weeks ago
- SystemRDL 2.0 language compiler front-end☆261Updated last week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆282Updated 2 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆267Updated last month
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆227Updated last week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆284Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆611Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated 2 weeks ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 11 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- PandA-bambu public repository☆289Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆474Updated this week
- Python wrapper for verilator model☆89Updated last year
- SystemVerilog frontend for Yosys☆165Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- ☆103Updated 3 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆305Updated 3 months ago
- FOSS Flow For FPGA☆407Updated 9 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 3 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated last week