phanrahan / magma
magma circuits
☆259Updated 6 months ago
Alternatives and similar repositories for magma:
Users that are interested in magma are comparing it to the libraries listed below
- SystemRDL 2.0 language compiler front-end☆250Updated last month
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆409Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆275Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆250Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated 3 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆247Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆388Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆475Updated 2 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆210Updated 4 months ago
- SystemVerilog synthesis tool☆189Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆567Updated this week
- An abstraction library for interfacing EDA tools☆681Updated last week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆443Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆433Updated last month
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆291Updated last month
- SystemVerilog to Verilog conversion☆615Updated 2 weeks ago
- ☆102Updated 2 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆313Updated this week
- Build Customized FPGA Implementations for Vivado☆313Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated last month
- Code generation tool for control and status registers☆380Updated 2 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆220Updated this week
- VeeR EL2 Core☆273Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆270Updated last week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆134Updated 6 months ago
- Network on Chip Implementation written in SytemVerilog☆172Updated 2 years ago
- Python-based hardware modeling framework☆239Updated 5 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 5 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆224Updated 5 months ago
- ☆318Updated 7 months ago