leonardt / faultLinks
A Python package for testing hardware (part of the magma ecosystem)
☆43Updated last year
Alternatives and similar repositories for fault
Users that are interested in fault are comparing it to the libraries listed below
Sorting:
- ☆31Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- mantle library☆44Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆37Updated last week
- A SystemVerilog source file pickler.☆57Updated 7 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Announcements related to Verilator☆39Updated 5 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆35Updated last week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆59Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆58Updated 4 months ago
- Python interface for cross-calling with HDL☆32Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆121Updated this week
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Running Python code in SystemVerilog☆69Updated this week
- ☆54Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 8 months ago
- ☆56Updated 2 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆52Updated last year
- Hardware generator debugger☆74Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆24Updated 3 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆43Updated 4 months ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated 2 weeks ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆60Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ☆95Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year