Alternatives and similar repositories for fault:

Users that are interested in fault are comparing it to the libraries listed below

• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 7 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• aolofsson / POSH
  ☆40Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆87Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 4 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆30Updated this week
• phanrahan / mantle
  mantle library
  ☆42Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated last week
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆24Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• idea-fasoc / fasoc
  ☆53Updated last year
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 5 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆74Updated 3 months ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆116Updated 4 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆79Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated 3 weeks ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆36Updated 8 years ago
• chipsalliance / fpga-interchange-schema
  ☆54Updated 2 years ago