leonardt / faultLinks
A Python package for testing hardware (part of the magma ecosystem)
☆46Updated last year
Alternatives and similar repositories for fault
Users that are interested in fault are comparing it to the libraries listed below
Sorting:
- Tools for working with circuits as graphs in python☆126Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last week
- hardware library for hwt (= ipcore repo)☆43Updated last week
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- ☆56Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆67Updated 2 years ago
- ☆43Updated 7 years ago
- Python wrapper for verilator model☆92Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆49Updated 4 years ago
- ☆44Updated 5 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆48Updated last year
- Python library for operations with VCD and other digital wave files☆53Updated last week
- A SystemVerilog source file pickler.☆60Updated last year
- Open source RTL simulation acceleration on commodity hardware☆32Updated 2 years ago
- ☆33Updated 10 months ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 9 months ago
- An automatic clock gating utility☆51Updated 7 months ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- BAG framework☆41Updated last year
- ☆57Updated 3 years ago
- ideas and eda software for vlsi design☆50Updated this week
- ☆31Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- Python interface to FPGA interchange format☆41Updated 3 years ago