leonardt / fault
A Python package for testing hardware (part of the magma ecosystem)
☆41Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for fault
- ☆30Updated last year
- Running Python code in SystemVerilog☆63Updated 4 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated this week
- Announcements related to Verilator☆38Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- Builds, flow and designs for the alpha release☆53Updated 4 years ago
- Tools for working with circuits as graphs in python☆110Updated last year
- Python library for operations with VCD and other digital wave files☆47Updated 5 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆43Updated 3 years ago
- ☆39Updated 4 years ago
- mantle library☆42Updated last year
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆39Updated 6 years ago
- A SystemVerilog source file pickler.☆52Updated last month
- AMC: Asynchronous Memory Compiler☆46Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- hardware library for hwt (= ipcore repo)☆34Updated this week
- Constrained RAndom Verification Enviroment (CRAVE)☆16Updated 11 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- Python wrapper for verilator model☆78Updated 9 months ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆18Updated 5 years ago
- ☆52Updated last year
- ☆66Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆42Updated last month
- Python packages providing a library for Verification Stimulus and Coverage☆114Updated 2 months ago
- ☆75Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 weeks ago
- ideas and eda software for vlsi design☆47Updated this week