leonardt / hwtypesLinks
Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
☆18Updated last year
Alternatives and similar repositories for hwtypes
Users that are interested in hwtypes are comparing it to the libraries listed below
Sorting:
- The PE for the second generation CGRA (garnet).☆17Updated 2 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆43Updated last year
- Cross EDA Abstraction and Automation☆39Updated 2 weeks ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆41Updated last month
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 5 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- Fast PnR toolchain for CGRA☆18Updated 11 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆13Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- An abstract language model of SystemVerilog (incl. Verilog) written in Python.☆9Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 9 months ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- mantle library☆44Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- Benchmarks for Yosys development☆24Updated 5 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Bitstream Fault Analysis Tool☆14Updated last year
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- A framework for FPGA emulation of mixed-signal systems☆36Updated 3 years ago
- ☆13Updated 4 years ago