leonardt / hwtypes
Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
☆18Updated last year
Alternatives and similar repositories for hwtypes:
Users that are interested in hwtypes are comparing it to the libraries listed below
- The PE for the second generation CGRA (garnet).☆17Updated this week
- Collection of test cases for Yosys☆18Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Cross EDA Abstraction and Automation☆36Updated last week
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆41Updated last year
- Automatic generation of real number models from analog circuits☆39Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 4 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 6 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 3 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆20Updated 3 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated last year
- An abstract language model of SystemVerilog (incl. Verilog) written in Python.☆9Updated last week
- A framework for FPGA emulation of mixed-signal systems☆35Updated 3 years ago
- ☆55Updated 2 years ago
- The test suite for the Xyce Parallel Electronic Simulator☆4Updated this week
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- Hardware Formal Verification☆15Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆22Updated 4 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- Python/Simulator integration using procedure calls☆9Updated 5 years ago
- BAG framework☆40Updated 8 months ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 7 months ago
- Provides a packaged collection of open source EDA tools☆12Updated 6 years ago