Alternatives and similar repositories for hwtypes

Users that are interested in hwtypes are comparing it to the libraries listed below

• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆46Updated last year
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 6 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated last week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 7 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated last week
• cdonovick / peak
  Peak : Processor Specification Language ala Newell and Bell's ISP
  ☆20Updated last year
• rdaly525 / coreir
  ☆104Updated 3 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆19Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated last week
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆57Updated 3 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆23Updated 5 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 3 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆27Updated last month
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• pulp-platform / ELAU
  ☆20Updated last year