dillonhuff / ahaHLSLinks
An open source high level synthesis (HLS) tool built on top of LLVM
☆127Updated last year
Alternatives and similar repositories for ahaHLS
Users that are interested in ahaHLS are comparing it to the libraries listed below
Sorting:
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆168Updated this week
- Next generation CGRA generator☆118Updated this week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- high-performance RTL simulator☆184Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- The Task Parallel System Composer (TaPaSCo)☆114Updated 3 weeks ago
- ☆87Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Python wrapper for verilator model☆92Updated last year
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Open-source RTL logic simulator with CUDA acceleration☆240Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 2 months ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- Algorithmic C Datatypes☆133Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- OpenSoC Fabric - A Network-On-Chip Generator☆174Updated 5 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆229Updated this week
- ☆104Updated 3 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆287Updated last month
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month