An open source high level synthesis (HLS) tool built on top of LLVM
☆127Jun 11, 2024Updated last year
Alternatives and similar repositories for ahaHLS
Users that are interested in ahaHLS are comparing it to the libraries listed below
Sorting:
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- Verilog AST☆20Dec 2, 2023Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- ☆105Jun 27, 2022Updated 3 years ago
- ☆87Mar 5, 2024Updated 2 years ago
- DASS HLS Compiler☆29Oct 4, 2023Updated 2 years ago
- Papers, Posters, Presentations, Documentation...☆19Jan 9, 2024Updated 2 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- PandA-bambu public repository☆314Feb 10, 2026Updated last month
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆171Updated this week
- ☆29Oct 4, 2017Updated 8 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- Next generation CGRA generator☆119Mar 13, 2026Updated last week
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Nov 15, 2022Updated 3 years ago
- Build Customized FPGA Implementations for Vivado☆356Mar 4, 2026Updated 2 weeks ago
- magma circuits☆265Oct 19, 2024Updated last year
- Languages, Tools, and Techniques for Accelerator Design☆33Nov 2, 2021Updated 4 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆340Apr 20, 2024Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆185Mar 8, 2026Updated last week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- Vitis HLS LLVM source code and examples☆406Sep 30, 2025Updated 5 months ago
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- Circuit IR Compilers and Tools☆2,065Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆54Jul 17, 2023Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆376Jan 20, 2025Updated last year
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 4 years ago
- A hardware synthesis framework with multi-level paradigm☆44Jan 10, 2025Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated last month
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Nov 7, 2023Updated 2 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆28Jan 21, 2026Updated last month
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆295Oct 30, 2025Updated 4 months ago