☆82Feb 7, 2025Updated last year
Alternatives and similar repositories for Halide-to-Hardware_archive
Users that are interested in Halide-to-Hardware_archive are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Next generation CGRA generator☆119Jul 16, 2026Updated last week
- ☆106Jun 27, 2022Updated 4 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- ☆62Jul 16, 2026Updated last week
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 5 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- HLS branch of Halide☆78Jul 6, 2018Updated 8 years ago
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Jul 16, 2026Updated last week
- ☆24Nov 10, 2020Updated 5 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- magma circuits☆264Oct 19, 2024Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆299Updated this week
- A home for Genesis2 sources.☆47Jun 15, 2026Updated last month
- ☆11Sep 14, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- Papers, Posters, Presentations, Documentation...☆20Jan 9, 2024Updated 2 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆243Dec 8, 2022Updated 3 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- This Is Indian Country - Spring 2018 Instance☆12Apr 30, 2018Updated 8 years ago
- An infrastructure for integrated EDA☆44Jul 20, 2023Updated 3 years ago
- Fibertree emulator☆17Nov 4, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"☆291Jun 2, 2024Updated 2 years ago
- CGRA Compilation Framework☆92Jul 15, 2023Updated 3 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆338Apr 20, 2024Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆130Jun 11, 2024Updated 2 years ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆608Updated this week
- Matrix Multiply and Accumulate unit written in System Verilog☆15Feb 7, 2019Updated 7 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆237Apr 13, 2026Updated 3 months ago
- ☆33Jul 22, 2020Updated 6 years ago
- Optimal approximate sampling from discrete probability distributions☆18Mar 9, 2021Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆45Jun 30, 2024Updated 2 years ago
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆67Oct 9, 2024Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆156Updated this week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- ☆13Jun 22, 2017Updated 9 years ago
- The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, mod…☆79Apr 24, 2020Updated 6 years ago