StanfordAHA / Halide-to-Hardware_archive
☆81Updated last month
Alternatives and similar repositories for Halide-to-Hardware_archive:
Users that are interested in Halide-to-Hardware_archive are comparing it to the libraries listed below
- HLS branch of Halide☆77Updated 6 years ago
- ☆55Updated this week
- Next generation CGRA generator☆109Updated this week
- A polyhedral compiler for hardware accelerators☆56Updated 7 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 4 years ago
- ☆91Updated last year
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆49Updated 6 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Project repo for the POSH on-chip network generator☆44Updated this week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 5 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆55Updated last month
- ☆102Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆87Updated last year
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 3 weeks ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆161Updated 3 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆96Updated last year
- MAERI public release☆31Updated 3 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- EQueue Dialect☆40Updated 3 years ago