StanfordAHA / Halide-to-Hardware_archiveLinks
☆81Updated 5 months ago
Alternatives and similar repositories for Halide-to-Hardware_archive
Users that are interested in Halide-to-Hardware_archive are comparing it to the libraries listed below
Sorting:
- HLS branch of Halide☆77Updated 7 years ago
- ☆59Updated this week
- Next generation CGRA generator☆112Updated this week
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- A polyhedral compiler for hardware accelerators☆59Updated 11 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Updated 6 years ago
- ☆86Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆106Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆125Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆92Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 2 weeks ago
- Falcon Merlin Compiler☆41Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago
- ☆103Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆75Updated 6 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆275Updated 2 months ago
- ☆88Updated 2 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆162Updated 3 years ago
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆213Updated 5 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Updated 6 years ago
- Stencil with Optimized Dataflow Architecture☆16Updated last year