Alternatives and similar repositories for hwt

Users that are interested in hwt are comparing it to the libraries listed below

• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆234Updated last month
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆235Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆261Updated last month
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆304Updated 3 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆127Updated last month
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆162Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 2 weeks ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 3 weeks ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated 3 weeks ago
• kevinpt / symbolator
  HDL symbol generator
  ☆195Updated 2 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆215Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆197Updated last week
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 5 months ago
• phanrahan / magma
  magma circuits
  ☆262Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆78Updated last week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆107Updated 3 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆296Updated 2 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago