VHDL/Verilog/SystemC code generator, simulator API written in python/c++
☆223Dec 23, 2025Updated 3 months ago
Alternatives and similar repositories for hwt
Users that are interested in hwt are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- hardware library for hwt (= ipcore repo)☆44Dec 23, 2025Updated 3 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆320Jun 30, 2025Updated 8 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- magma circuits☆265Oct 19, 2024Updated last year
- Streaming based VHDL parser.☆84Jul 15, 2024Updated last year
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆28Jan 21, 2026Updated 2 months ago
- Next generation CGRA generator☆119Updated this week
- A Hardware Construct Language☆44Jul 25, 2022Updated 3 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆446Mar 6, 2026Updated 2 weeks ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 4 months ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- 🔁 elastic circuit toolchain☆33Dec 2, 2024Updated last year
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 4 months ago
- Hardware Description Languages☆1,131Mar 17, 2026Updated last week
- Visual Simulation of Register Transfer Logic☆112Feb 14, 2026Updated last month
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated 2 weeks ago
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆297Mar 13, 2026Updated last week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆300Feb 17, 2026Updated last month
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆324Mar 8, 2026Updated 2 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated last month
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- D3.js and ELK based schematic visualizer☆116Feb 27, 2024Updated 2 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Oct 8, 2024Updated last year
- ☆105Jun 27, 2022Updated 3 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- ☆25Mar 17, 2026Updated last week
- Tools for working with circuits as graphs in python☆127Nov 17, 2023Updated 2 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Nov 12, 2025Updated 4 months ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- A Python toolbox for building complex digital hardware☆1,320Jan 5, 2026Updated 2 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆295Oct 30, 2025Updated 4 months ago
- HTML & Js based VCD viewer☆74Feb 16, 2026Updated last month
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year