Alternatives and similar repositories for hwt

Users that are interested in hwt are comparing it to the libraries listed below

• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆219Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆138Updated 2 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆224Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆300Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆141Updated 2 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated 2 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆256Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆152Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆162Updated 2 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 9 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆278Updated 5 years ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆80Updated 9 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆122Updated 8 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆73Updated 2 weeks ago
• phanrahan / magma
  magma circuits
  ☆261Updated 9 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆204Updated 4 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆193Updated 2 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆41Updated 2 weeks ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆133Updated last year
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆106Updated 4 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 5 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆76Updated 3 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆191Updated last week