Nic30 / hwtLinks
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
☆219Updated 2 weeks ago
Alternatives and similar repositories for hwt
Users that are interested in hwt are comparing it to the libraries listed below
Sorting:
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 2 months ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆238Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆131Updated 2 weeks ago
- A complete open-source design-for-testing (DFT) Solution☆169Updated 3 months ago
- SystemRDL 2.0 language compiler front-end☆266Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆309Updated 5 months ago
- FuseSoC standard core library☆149Updated 6 months ago
- Streaming based VHDL parser.☆84Updated last year
- Python-based IP-XACT parser☆142Updated last year
- Control and status register code generator toolchain☆155Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 3 weeks ago
- A curated list of awesome resources for HDL design and verification☆164Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- SystemVerilog synthesis tool☆219Updated 8 months ago
- hardware library for hwt (= ipcore repo)☆43Updated 3 weeks ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- magma circuits☆263Updated last year
- Simple parser for extracting VHDL documentation☆72Updated last year
- Announcements related to Verilator☆43Updated last month
- HDL symbol generator☆197Updated 2 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆117Updated 2 months ago
- ideas and eda software for vlsi design☆50Updated 2 weeks ago
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated 10 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- FPGA and Digital ASIC Build System☆80Updated 2 weeks ago
- SystemVerilog frontend for Yosys☆176Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆203Updated last year
- UVM 1.2 port to Python☆254Updated 9 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆297Updated 3 weeks ago
- Verilog digital signal processing components☆159Updated 3 years ago