Nic30 / hwtLinks
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
☆220Updated this week
Alternatives and similar repositories for hwt
Users that are interested in hwt are comparing it to the libraries listed below
Sorting:
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆240Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆310Updated 5 months ago
- HDL symbol generator☆200Updated 2 years ago
- FuseSoC standard core library☆150Updated 2 weeks ago
- SystemRDL 2.0 language compiler front-end☆268Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Python packages providing a library for Verification Stimulus and Coverage☆134Updated last month
- A curated list of awesome resources for HDL design and verification☆166Updated last week
- A complete open-source design-for-testing (DFT) Solution☆173Updated 3 months ago
- Control and status register code generator toolchain☆162Updated 3 weeks ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Python-based IP-XACT parser☆142Updated last year
- Streaming based VHDL parser.☆84Updated last year
- RISC-V Verification Interface☆132Updated 2 weeks ago
- hardware library for hwt (= ipcore repo)☆43Updated last month
- SystemVerilog frontend for Yosys☆184Updated this week
- magma circuits☆263Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆299Updated this week
- FPGA and Digital ASIC Build System☆80Updated last month
- Fabric generator and CAD tools.☆214Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Announcements related to Verilator☆43Updated last month
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆205Updated last year
- Simple parser for extracting VHDL documentation☆72Updated last year
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆104Updated 10 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago