A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
☆306Oct 26, 2026Updated this week
Alternatives and similar repositories for PyRTL
Users that are interested in PyRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Language for Closed-form High-level ARchitecture Modeling☆21Feb 10, 2020Updated 6 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆470Sep 10, 2026Updated last month
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆806Dec 6, 2017Updated 8 years ago
- Python-based hardware modeling framework☆247Oct 27, 2019Updated 7 years ago
- magma circuits☆264Oct 19, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Oct 16, 2026Updated 2 weeks ago
- The MyHDL development repository☆1,131Sep 14, 2026Updated last month
- DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework☆99Sep 8, 2026Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆329Aug 7, 2026Updated 2 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆252Updated this week
- Verilog AST☆19Dec 2, 2023Updated 2 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- A simple library operating system in Rust☆10Aug 4, 2017Updated 9 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Hardware Description Languages☆1,184Jul 9, 2026Updated 3 months ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆327Mar 8, 2026Updated 7 months ago
- A Python toolbox for building complex digital hardware☆1,330Jan 5, 2026Updated 9 months ago
- Hardware Description Library☆96Feb 17, 2026Updated 8 months ago
- ☆106Jun 27, 2022Updated 4 years ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- high-performance RTL simulator☆196Aug 4, 2026Updated 2 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Cross EDA Abstraction and Automation☆45Updated this week
- Designs, infrastructure, and experiments around Race Logic☆26Jun 25, 2020Updated 6 years ago
- Next generation CGRA generator☆119Updated this week
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated 2 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆14Mar 27, 2025Updated last year
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 9 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆300Jun 18, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- A modern hardware definition language and toolchain based on Python☆2,119Sep 18, 2026Updated last month
- SystemVerilog to Verilog conversion☆758Aug 18, 2026Updated 2 months ago
- XLS: Accelerated HW Synthesis☆1,969Updated this week
- An open-source static random access memory (SRAM) compiler.☆1,169Updated this week
- Modular hardware build system☆1,239Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week