Alternatives and similar repositories for PyRTL

Users that are interested in PyRTL are comparing it to the libraries listed below

• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆278Updated this week
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆239Updated 5 years ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆409Updated last week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆315Updated this week
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆209Updated 5 years ago
• phanrahan / magma
  magma circuits
  ☆260Updated 6 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 3 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆253Updated last week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆211Updated 5 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated last week
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆369Updated this week
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆136Updated 7 months ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆237Updated last year
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆268Updated 2 weeks ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆251Updated 2 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆421Updated last month
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆222Updated this week
• ucb-bar / berkeley-hardfloat
  ☆322Updated 8 months ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆205Updated 9 months ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆707Updated 10 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆291Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆190Updated 2 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆158Updated 10 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆275Updated 2 weeks ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆209Updated 6 months ago
• chipsalliance / VeeR-ISS
  ☆134Updated last year
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆135Updated 5 years ago