A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
☆304Oct 7, 2026Updated this week
Alternatives and similar repositories for PyRTL
Users that are interested in PyRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Language for Closed-form High-level ARchitecture Modeling☆21Feb 10, 2020Updated 6 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆468Sep 10, 2026Updated last month
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆792Dec 6, 2017Updated 8 years ago
- Python-based hardware modeling framework☆247Oct 27, 2019Updated 6 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Sep 20, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- magma circuits☆264Oct 19, 2024Updated last year
- DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework☆98Sep 8, 2026Updated last month
- The MyHDL development repository☆1,131Sep 14, 2026Updated 3 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆328Aug 7, 2026Updated 2 months ago
- Cross EDA Abstraction and Automation☆43Updated this week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- Next generation CGRA generator☆119Updated this week
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 3 years ago
- ☆106Jun 27, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- A Python toolbox for building complex digital hardware☆1,330Jan 5, 2026Updated 9 months ago
- Hardware Description Library☆96Feb 17, 2026Updated 7 months ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- Verilog AST☆19Dec 2, 2023Updated 2 years ago
- Designs, infrastructure, and experiments around Race Logic☆26Jun 25, 2020Updated 6 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆242Updated this week
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆327Mar 8, 2026Updated 7 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Hardware Description Languages☆1,181Jul 9, 2026Updated 3 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- 🔁 elastic circuit toolchain☆33Jul 20, 2026Updated 2 months ago
- high-performance RTL simulator☆196Aug 4, 2026Updated 2 months ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 6 months ago
- SystemVerilog to Verilog conversion☆754Aug 18, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆689Sep 28, 2026Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- A modern hardware definition language and toolchain based on Python☆2,104Sep 18, 2026Updated 3 weeks ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago