UCSBarchlab / PyRTLLinks
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research.  Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
☆289Updated this week
Alternatives and similar repositories for PyRTL
Users that are interested in PyRTL are comparing it to the libraries listed below
Sorting:
- magma circuits☆262Updated last year
 - Python-based hardware modeling framework☆244Updated 6 years ago
 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆432Updated 2 months ago
 - Hammer: Highly Agile Masks Made Effortlessly from RTL☆300Updated 3 weeks ago
 - SystemC/C++ library of commonly-used hardware functions and components for HLS.☆285Updated this week
 - Tile based architecture designed for computing efficiency, scalability and generality☆272Updated last month
 - Python wrapper for verilator model☆92Updated last year
 - Build Customized FPGA Implementations for Vivado☆341Updated this week
 - PandA-bambu public repository☆292Updated last month
 - Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆217Updated 5 years ago
 - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆387Updated 2 weeks ago
 - An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
 - Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated last year
 - mflowgen -- A Modular ASIC/FPGA Flow Generator☆271Updated 2 weeks ago
 - A dynamic verification library for Chisel.☆157Updated 11 months ago
 - Next generation CGRA generator☆115Updated this week
 - ☆350Updated last month
 - A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
 - high-performance RTL simulator☆181Updated last year
 - A Library of Chisel3 Tools for Digital Signal Processing☆240Updated last year
 - SystemVerilog synthesis tool☆216Updated 7 months ago
 - Chisel components for FPGA projects☆127Updated 2 years ago
 - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆226Updated last week
 - RISC-V Torture Test☆200Updated last year
 - Code used in☆198Updated 8 years ago
 - VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆218Updated last week
 - Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
 - HW Design: A Functional Approach☆146Updated 2 years ago
 - OpenSoC Fabric - A Network-On-Chip Generator☆173Updated 5 years ago
 - Open-source RTL logic simulator with CUDA acceleration☆231Updated last month