UCSBarchlab / PyRTLLinks
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
☆293Updated last month
Alternatives and similar repositories for PyRTL
Users that are interested in PyRTL are comparing it to the libraries listed below
Sorting:
- magma circuits☆264Updated last year
- Python-based hardware modeling framework☆245Updated 6 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆439Updated 4 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆308Updated 3 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆290Updated 2 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆219Updated 5 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated last month
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Python wrapper for verilator model☆92Updated last year
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆398Updated 2 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆175Updated 5 years ago
- Build Customized FPGA Implementations for Vivado☆352Updated this week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Updated 2 weeks ago
- Next generation CGRA generator☆118Updated last week
- high-performance RTL simulator☆184Updated last year
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- RISC-V Virtual Prototype☆183Updated last year
- HW Design: A Functional Approach☆145Updated 2 years ago
- PandA-bambu public repository☆303Updated 2 weeks ago
- ☆362Updated 3 months ago
- SystemVerilog synthesis tool☆223Updated 10 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆230Updated this week
- A dynamic verification library for Chisel.☆159Updated last year
- Vitis HLS LLVM source code and examples☆403Updated 3 months ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- Bluespec BSV HLHDL tutorial☆110Updated 9 years ago
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆233Updated this week