Alternatives and similar repositories for pymtl

Users that are interested in pymtl are comparing it to the libraries listed below

• UCSBarchlab / PyRTL
  A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…
  ☆294Updated 2 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆221Updated 6 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆292Updated 3 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆442Updated 5 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆308Updated 3 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆355Updated last week
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆175Updated 5 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆221Updated last month
• ferrandi / PandA-bambu
  PandA-bambu public repository
  ☆307Updated last week
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆183Updated last year
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆145Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆403Updated 4 months ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆264Updated 8 months ago
• ucb-bar / berkeley-hardfloat
  ☆365Updated 4 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆275Updated 3 weeks ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆106Updated 7 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆270Updated 2 weeks ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆400Updated 3 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆300Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆239Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• subbdue / systemverilog.io
  Code used in
  ☆201Updated 8 years ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆172Updated this week