Alternatives and similar repositories for pymtl:

Users that are interested in pymtl are comparing it to the libraries listed below

• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆308Updated this week
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆210Updated 5 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆265Updated 4 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆268Updated 2 weeks ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆166Updated last year
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆164Updated 4 years ago
• phanrahan / magma
  magma circuits
  ☆259Updated 5 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆133Updated 6 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆407Updated 2 weeks ago
• UCSBarchlab / PyRTL
  A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…
  ☆269Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆562Updated last week
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆101Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆173Updated 3 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆208Updated 4 months ago
• ucb-bar / berkeley-hardfloat
  ☆310Updated 6 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆246Updated last month
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆344Updated 7 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆411Updated 2 weeks ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆363Updated 2 weeks ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆234Updated 10 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆198Updated 5 months ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆408Updated 6 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆107Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆223Updated 4 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆267Updated last week
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆163Updated last month
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆289Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆309Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆529Updated last month