phanrahan / magmathon
Magma Hackathon
☆11Updated 4 years ago
Related projects: ⓘ
- mantle library☆42Updated last year
- Loam system models☆16Updated 4 years ago
- FuseSoc Verification Automation☆21Updated 2 years ago
- A padring generator for ASICs☆22Updated last year
- 👾 Design ∪ Hardware☆72Updated 11 months ago
- ☆22Updated 11 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 2 months ago
- Virtual development board for HDL design☆38Updated last year
- Cross EDA Abstraction and Automation☆33Updated last week
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆45Updated 3 months ago
- Small footprint and configurable Inter-Chip communication cores☆53Updated this week
- Digital Circuit rendering engine☆31Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆48Updated 8 months ago
- USB virtual model in C++ for Verilog☆26Updated 2 weeks ago
- Provides automation scripts for building BFMs☆15Updated 2 years ago
- Atom Hardware IDE☆13Updated 3 years ago
- A tool for merging the MyHDL workflow with Vivado☆19Updated 4 years ago
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆25Updated last year
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- ☆20Updated this week
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- ☆31Updated last year
- 🔍 Zoomable Waveform viewer for the Web☆43Updated 3 years ago
- ☆29Updated 3 years ago
- Xilinx Unisim Library in Verilog☆68Updated 4 years ago
- VHDL dependency analyzer☆21Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆68Updated 2 years ago