Alternatives and similar repositories for magmathon

Users that are interested in magmathon are comparing it to the libraries listed below

• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• phanrahan / loam
  Loam system models
  ☆16Updated 5 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 3 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 3 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆87Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆22Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated 2 weeks ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆63Updated 2 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆64Updated last month
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 4 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• jkorinth / chisel-packaging
  IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.
  ☆11Updated 6 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆48Updated 5 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆47Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last week