phanrahan / mantleLinks
mantle library
☆44Updated 2 years ago
Alternatives and similar repositories for mantle
Users that are interested in mantle are comparing it to the libraries listed below
Sorting:
- ☆23Updated 5 months ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- ☆38Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- System on Chip toolkit for Amaranth HDL☆95Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Prefix tree adder space exploration library☆56Updated 11 months ago
- Debuggable hardware generator☆70Updated 2 years ago
- ☆38Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- PicoRV☆43Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- ☆85Updated last week
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 9 months ago
- An automatic clock gating utility☆50Updated 6 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- Magma Hackathon☆12Updated 5 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- Visual Simulation of Register Transfer Logic☆102Updated 2 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- USB virtual model in C++ for Verilog☆32Updated last year
- Digital Circuit rendering engine☆39Updated 2 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated last month