phanrahan / mantle
mantle library
☆44Updated 2 years ago
Alternatives and similar repositories for mantle:
Users that are interested in mantle are comparing it to the libraries listed below
- ☆36Updated 2 years ago
- Debuggable hardware generator☆68Updated 2 years ago
- Xilinx Unisim Library in Verilog☆75Updated 4 years ago
- SystemVerilog frontend for Yosys☆81Updated 2 weeks ago
- A Python package for testing hardware (part of the magma ecosystem)☆41Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆80Updated 2 weeks ago
- A SystemVerilog source file pickler.☆56Updated 5 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 6 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆25Updated 4 years ago
- An automatic clock gating utility☆45Updated 8 months ago
- Magma Hackathon☆12Updated 5 years ago
- ☆22Updated last year
- Hardware generator debugger☆73Updated last year
- Benchmarks for Yosys development☆23Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- ☆33Updated 4 years ago
- ☆31Updated 2 months ago
- ☆34Updated this week
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 8 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- ☆55Updated 2 years ago
- ☆31Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Digital Circuit rendering engine☆38Updated last year
- A padring generator for ASICs☆25Updated last year