cdonovick / peak

Related projects: ⓘ

• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆16Updated 2 weeks ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆61Updated 3 years ago
• rdaly525 / coreir
  ☆99Updated 2 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆32Updated 2 years ago
• StanfordAHA / CGRAGenerator
  ☆19Updated this week
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆17Updated this week
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 4 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆17Updated last month
• chipsalliance / fpga-interchange-schema
  ☆51Updated 2 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆39Updated 10 months ago
• vegaluisjose / vast
  Verilog AST
  ☆19Updated 9 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆93Updated last month
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated last year
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆104Updated this week
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆75Updated 2 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆33Updated last year
• David-Durst / embeddedHaskellAetherling
  ☆24Updated last year
• StanfordAHA / aha
  ☆46Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 7 months ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆30Updated 5 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆29Updated 3 years ago
• vegaluisjose / reticle
  ☆41Updated 3 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆18Updated 4 months ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated last month
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 2 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆36Updated last year
• StanfordAHA / doc
  Papers, Posters, Presentations, Documentation...
  ☆18Updated 8 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆20Updated 3 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆55Updated 4 years ago