Peak : Processor Specification Language ala Newell and Bell's ISP
☆20Dec 5, 2023Updated 2 years ago
Alternatives and similar repositories for peak
Users that are interested in peak are comparing it to the libraries listed below
Sorting:
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last week
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- ☆104Jun 27, 2022Updated 3 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- CoreIR Symbolic Analyzer☆74Oct 27, 2020Updated 5 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- Next generation CGRA generator☆118Feb 14, 2026Updated 2 weeks ago
- magma circuits☆265Oct 19, 2024Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 2 years ago
- ☆82Feb 7, 2025Updated last year
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- ☆62Feb 23, 2026Updated last week
- ☆15Mar 6, 2021Updated 4 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆23Jun 30, 2024Updated last year
- Toolbox for working with the Python AST☆16Sep 13, 2023Updated 2 years ago
- A home for Genesis2 sources.☆44Updated this week
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Oct 31, 2017Updated 8 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆27Jan 21, 2026Updated last month
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Feb 8, 2026Updated 3 weeks ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- Creating beautiful gem5 simulations☆49Mar 22, 2021Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- Pono: A flexible and extensible SMT-based model checker☆117Feb 5, 2026Updated 3 weeks ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆57Sep 15, 2020Updated 5 years ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- A heuristic procedure for proving inequalities☆34Sep 4, 2018Updated 7 years ago
- ☆30Oct 16, 2022Updated 3 years ago
- ☆28Nov 20, 2025Updated 3 months ago
- A machine model for line-rate programmable switches☆26Oct 8, 2016Updated 9 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- The Domino compiler to run packet programs on pipelined switches☆29Aug 12, 2021Updated 4 years ago
- A parallel, distributed simulator for multicores.☆185Nov 19, 2015Updated 10 years ago