Alternatives and similar repositories for peak

Users that are interested in peak are comparing it to the libraries listed below

• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 weeks ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆72Updated 4 years ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated this week
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆21Updated 6 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated 9 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated this week
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆26Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆18Updated 9 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 3 years ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated last year