Alternatives and similar repositories for peak

Users that are interested in peak are comparing it to the libraries listed below

• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 3 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last month
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆110Updated 2 months ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆23Updated 4 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last week
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆113Updated last week
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 3 weeks ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• zhemao / creek
  A vector processor implemented in Chisel
  ☆21Updated 11 years ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆39Updated 3 weeks ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated this week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago