Alternatives and similar repositories for hdlConvertor

Users that are interested in hdlConvertor are comparing it to the libraries listed below

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆439Updated 4 months ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆242Updated last week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆270Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆357Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆245Updated 4 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆259Updated 11 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆137Updated 2 weeks ago
• svunit / svunit
  ☆208Updated 10 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆206Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆167Updated 2 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆497Updated last week
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated 2 years ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆285Updated 6 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆355Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 4 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆441Updated 3 weeks ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆148Updated 11 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆300Updated 2 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆308Updated 4 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆226Updated 10 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆309Updated 3 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆178Updated 5 months ago
• olofk / ipyxact
  Python-based IP-XACT parser and utilities
  ☆143Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆641Updated 2 weeks ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆166Updated last month
• raysalemi / Python4RTLVerification
  ☆174Updated 3 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆253Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆134Updated 6 years ago