Alternatives and similar repositories for hdlConvertor

Users that are interested in hdlConvertor are comparing it to the libraries listed below

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆407Updated 3 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆257Updated 3 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆338Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated 3 weeks ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆222Updated last week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 6 months ago
• svunit / svunit
  ☆206Updated 5 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆335Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆279Updated 5 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆449Updated last month
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆215Updated last month
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆286Updated 3 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 6 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆813Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆276Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 10 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆282Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆208Updated 5 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆418Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆598Updated last week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆464Updated 2 weeks ago
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆161Updated 2 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated 2 weeks ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated 3 weeks ago