Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
☆331Jun 30, 2025Updated last year
Alternatives and similar repositories for hdlConvertor
Users that are interested in hdlConvertor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Simple parser for extracting VHDL documentation☆74Jul 12, 2024Updated 2 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Jul 23, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆471Jul 28, 2026Updated last week
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog compiler and language services☆1,107Updated this week
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆785Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆797Jun 15, 2024Updated 2 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆481Jun 10, 2026Updated 2 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆266Jul 22, 2026Updated 2 weeks ago
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated last month
- Repurposing existing HDL tools to help writing better code☆226Jun 21, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,904Updated this week
- HDL symbol generator☆205Feb 2, 2023Updated 3 years ago
- Web-based HDL diagramming tool☆86May 1, 2023Updated 3 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆239Updated this week
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- draws an SVG schematic from a JSON netlist☆812Jan 25, 2024Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- SystemVerilog to Verilog conversion☆747Mar 28, 2026Updated 4 months ago
- hardware library for hwt (= ipcore repo)☆45Jul 23, 2026Updated 2 weeks ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Cross EDA Abstraction and Automation☆42Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆147Jul 5, 2026Updated last month
- D3.js and ELK based schematic visualizer☆122May 13, 2026Updated 2 months ago
- VHDL related news.☆27Updated this week
- Python bindings for slang, a library for compiling SystemVerilog☆67Jan 18, 2025Updated last year
- cocotb: Python-based chip (RTL) verification☆2,471Updated this week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆843May 14, 2026Updated 2 months ago
- Python library for operations with VCD and other digital wave files☆55May 19, 2026Updated 2 months ago
- ☆144Feb 16, 2026Updated 5 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 6 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆457Apr 22, 2026Updated 3 months ago
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 3 years ago
- Hardware Description Languages☆1,165Jul 9, 2026Updated last month
- magma circuits☆265Oct 19, 2024Updated last year
- The UVM written in Python☆564Updated this week
- Building and deploying container images for open source electronic design automation (EDA)☆123Oct 3, 2024Updated last year