C++17 implementation of an AST for Verilog code generation
☆24Jun 14, 2023Updated 2 years ago
Alternatives and similar repositories for verilogAST-cpp
Users that are interested in verilogAST-cpp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Toolbox for working with the Python AST☆16Sep 13, 2023Updated 2 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- Magma Hackathon☆12Mar 4, 2020Updated 6 years ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- magma circuits☆265Oct 19, 2024Updated last year
- parser combinator and AST generator in c++17☆24Feb 16, 2023Updated 3 years ago
- FPGA related files for ORAM☆14Sep 23, 2015Updated 10 years ago
- ☆16Oct 25, 2022Updated 3 years ago
- Next generation CGRA generator☆119Mar 26, 2026Updated 2 weeks ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- [FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs☆25Feb 14, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Simulate System76 EC with area8051 emulator☆12Mar 2, 2024Updated 2 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- Digital Circuit rendering engine☆39Mar 31, 2026Updated last week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- The source code to the Voss II Hardware Verification Suite☆57Apr 2, 2026Updated last week
- Open Source PHY v2☆34Apr 25, 2024Updated last year
- A OpenCL-based FPGA benchmark suite for HPC☆37Jan 29, 2026Updated 2 months ago
- A template set for writing semantics in LaTeX☆12Aug 17, 2015Updated 10 years ago
- C++ Memory allocator for packet queues that free() in roughly the same order that they alloc().☆16Mar 15, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Repo manifest files for Mentor Embedded release of Android for Xilinx Zynq UltraScale+ MPSoC☆16Sep 11, 2020Updated 5 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆18Mar 29, 2021Updated 5 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Apr 17, 2016Updated 9 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- Automatic generation of real number models from analog circuits☆48Apr 2, 2024Updated 2 years ago
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 4 months ago
- Various test models in WNNX format. It can view with `pip install wnetron && wnetron`☆12Jun 22, 2022Updated 3 years ago
- Built a test environment using UVM Methodology to verify APB Protocol.☆15Feb 6, 2019Updated 7 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆15Apr 2, 2026Updated last week
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆41Aug 15, 2025Updated 7 months ago
- ☆14Feb 14, 2022Updated 4 years ago
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- Data structures for ASTs☆14Dec 6, 2022Updated 3 years ago
- SYCL-based Stencil Simulation Framework Targeting FPGAs☆17Aug 31, 2024Updated last year
- chipy hdl☆17Apr 5, 2018Updated 8 years ago