leonardt / verilogAST-cppLinks
C++17 implementation of an AST for Verilog code generation
☆24Updated 2 years ago
Alternatives and similar repositories for verilogAST-cpp
Users that are interested in verilogAST-cpp are comparing it to the libraries listed below
Sorting:
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- ☆15Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 8 months ago
- ☆27Updated 7 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆33Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Next generation CGRA generator☆112Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- A polyhedral compiler for hardware accelerators☆59Updated 11 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last week
- ☆103Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Floating point modules for CHISEL☆32Updated 10 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆22Updated 8 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆41Updated last month
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- ☆44Updated 5 years ago
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆111Updated last year
- Parsing library for BLIF netlists☆19Updated 7 months ago
- The PE for the second generation CGRA (garnet).☆17Updated 2 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- DASS HLS Compiler☆29Updated last year