👾 Design ∪ Hardware
☆79Sep 17, 2026Updated last month
Alternatives and similar repositories for duh
Users that are interested in duh are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wake build descriptions of hardware generators☆12Dec 11, 2020Updated 5 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- Workspace Integration Tool☆23Nov 6, 2020Updated 5 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆36Sep 30, 2020Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Oct 7, 2026Updated 3 weeks ago
- VHDLproc is a VHDL preprocessor☆25May 12, 2022Updated 4 years ago
- magma circuits☆264Oct 19, 2024Updated 2 years ago
- verilator testbench w/ Javascript using N-API☆18Feb 19, 2026Updated 8 months ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- The SiFive wake build tool☆95Oct 22, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 4 years ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 6 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- ☆16Aug 21, 2019Updated 7 years ago
- (System)Verilog to Chisel translator☆123May 20, 2022Updated 4 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Oct 16, 2026Updated 2 weeks ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆13Feb 13, 2021Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated last month
- Everything needed for ulx3s FPGA☆16Oct 12, 2020Updated 6 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- Cross EDA Abstraction and Automation☆45Updated this week
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- ☆106Jun 27, 2022Updated 4 years ago
- IP-XACT packaging of Pulpino by pulp-platform.org: https://github.com/pulp-platform/pulpino☆11Dec 11, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated this week
- SystemVerilog grammar for tree-sitter☆124Sep 13, 2026Updated last month
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆91Apr 13, 2026Updated 6 months ago
- Python library for operations with VCD and other digital wave files☆55May 19, 2026Updated 5 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago