Alternatives and similar repositories for netlistDB

Users that are interested in netlistDB are comparing it to the libraries listed below

• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last month
• aolofsson / POSH
  ☆44Updated 5 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 3 weeks ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 3 weeks ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 7 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆26Updated 2 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆29Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆38Updated this week
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 7 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 3 weeks ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆43Updated 3 weeks ago