netlistDB - Intermediate format for digital hardware representation with graph database API
☆31Mar 17, 2021Updated 5 years ago
Alternatives and similar repositories for netlistDB
Users that are interested in netlistDB are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- ☆16Apr 30, 2021Updated 5 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆332Jun 30, 2025Updated last year
- EDA physical synthesis optimization kit☆69Nov 13, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆29Updated this week
- Tools for working with circuits as graphs in python☆131Nov 17, 2023Updated 2 years ago
- Object-Oriented Programming☆12Aug 26, 2021Updated 5 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- ☆30Oct 2, 2023Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆45Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- IP-XACT XML binding library☆17Jun 23, 2016Updated 10 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆38Mar 7, 2026Updated 5 months ago
- Constrained random stimuli generation for C++ and SystemC☆53Nov 29, 2023Updated 2 years ago
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 9 months ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- ChipTools is a utility to automate FPGA build and verification☆26Oct 22, 2021Updated 4 years ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆116Apr 27, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆472Updated this week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- Initial 0.0.1 push☆13Jun 10, 2016Updated 10 years ago
- ☆13Jun 21, 2026Updated 2 months ago
- magma circuits☆265Oct 19, 2024Updated last year
- DyRACT Open Source Repository☆16May 4, 2016Updated 10 years ago
- Python library for operations with VCD and other digital wave files☆55May 19, 2026Updated 3 months ago
- A C++ -based STIL parser.☆12Apr 29, 2021Updated 5 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆267Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated last month
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontroller…☆11Jul 21, 2020Updated 6 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- ☆43May 26, 2018Updated 8 years ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 9 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆27May 23, 2024Updated 2 years ago