Alternatives and similar repositories for netlistDB:

Users that are interested in netlistDB are comparing it to the libraries listed below

• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated 4 months ago
• aolofsson / POSH
  ☆41Updated 5 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 3 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 8 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last week
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆14Updated 8 years ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆81Updated 5 months ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆31Updated last week
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆40Updated last month
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆64Updated 4 years ago
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆50Updated last year
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆68Updated 2 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆24Updated 2 years ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago