HardwareIR / netlistDBLinks
netlistDB - Intermediate format for digital hardware representation with graph database API
☆31Updated 4 years ago
Alternatives and similar repositories for netlistDB
Users that are interested in netlistDB are comparing it to the libraries listed below
Sorting:
- Collection of test cases for Yosys☆18Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Parsing library for BLIF netlists☆19Updated 10 months ago
- ☆44Updated 5 years ago
- An advanced header-only exact synthesis library☆27Updated 2 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆45Updated last year
- ☆31Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 2 months ago
- Debuggable hardware generator☆69Updated 2 years ago
- Simple UVM environment for experimenting with Verilator.☆23Updated 4 months ago
- The PE for the second generation CGRA (garnet).☆17Updated 4 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆86Updated 11 months ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 4 months ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- ☆56Updated 3 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Useful utilities for BAR projects☆32Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- Constrained random stimuli generation for C++ and SystemC☆52Updated last year
- FPGA tool performance profiling☆102Updated last year
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆35Updated 2 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- An infrastructure for integrated EDA☆41Updated 2 years ago
- ☆103Updated 3 years ago