Alternatives and similar repositories for netlistDB

Users that are interested in netlistDB are comparing it to the libraries listed below

• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 9 months ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 2 weeks ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆83Updated 9 months ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆37Updated 8 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆23Updated 3 months ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 3 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆34Updated 3 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆109Updated 2 months ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆31Updated 11 months ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆37Updated last year
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 8 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆22Updated 9 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago