Alternatives and similar repositories for netlistDB

Users that are interested in netlistDB are comparing it to the libraries listed below

• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated this week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆46Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 10 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 2 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 6 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆126Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated last month
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆31Updated last year
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆25Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆116Updated last week
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆31Updated 4 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago