HardwareIR / netlistDBLinks
netlistDB - Intermediate format for digital hardware representation with graph database API
☆32Updated 4 years ago
Alternatives and similar repositories for netlistDB
Users that are interested in netlistDB are comparing it to the libraries listed below
Sorting:
- Collection of test cases for Yosys☆17Updated 3 years ago
- An advanced header-only exact synthesis library☆29Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 10 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- Parsing library for BLIF netlists☆19Updated last year
- The Shang high-level synthesis framework☆120Updated 11 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated this week
- The PE for the second generation CGRA (garnet).☆17Updated 7 months ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- ☆104Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆44Updated 5 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Updated 3 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Updated last year
- Debuggable hardware generator☆70Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Useful utilities for BAR projects☆32Updated last year
- ☆31Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 6 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆150Updated 3 weeks ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- FPGA tool performance profiling☆103Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆22Updated 2 years ago
- Intel Compiler for SystemC☆26Updated 2 years ago