phanrahan / loam

Related projects: ⓘ

• phanrahan / magmathon
  Magma Hackathon
  ☆11Updated 4 years ago
• phanrahan / mantle
  mantle library
  ☆42Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• m-kru / fsva
  FuseSoc Verification Automation
  ☆21Updated 2 years ago
• kactus2 / ipxactexamplelib
  Contains examples to start with Kactus2.
  ☆15Updated last month
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 3 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆31Updated last year
• Nic30 / sphinx-hwt
  Sphinx extension for visual documentation of hardware written in HWT
  ☆11Updated 3 months ago
• hgomersall / Veriutils
  Verification Utilities for MyHDL
  ☆17Updated 10 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 11 months ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆15Updated 2 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆19Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆26Updated 2 weeks ago
• mattvenn / gtkwave-python-filter-process
  ☆29Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆35Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆34Updated last year
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆36Updated 10 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 5 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆38Updated last year
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆26Updated last year
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆19Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 6 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆33Updated last week
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆14Updated 5 months ago
• albaEDA / Nirah
  Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…
  ☆12Updated 5 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 3 years ago