Alternatives and similar repositories for loam

Users that are interested in loam are comparing it to the libraries listed below

• phanrahan / magmathon
  Magma Hackathon
  ☆12Updated 5 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 4 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• hgomersall / Veriutils
  Verification Utilities for MyHDL
  ☆17Updated last year
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated last year
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 3 weeks ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated 9 months ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• LaurentCabaret / pyVhdl2Sch
  pyVhdl2sch is a python based VHDL to (pdf) schematic converter
  ☆32Updated 5 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 10 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 2 months ago
• xobs / coriolis
  An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.
  ☆11Updated 6 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated last week
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆22Updated last year
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆28Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago