phanrahan / loamLinks
Loam system models
☆16Updated 5 years ago
Alternatives and similar repositories for loam
Users that are interested in loam are comparing it to the libraries listed below
Sorting:
- mantle library☆44Updated 2 years ago
- Magma Hackathon☆12Updated 5 years ago
- Verification Utilities for MyHDL☆17Updated 2 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Digital Circuit rendering engine☆39Updated 4 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Updated 5 years ago
- ☆38Updated 3 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Updated 3 years ago
- GUI editor for hardware description designs☆30Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆63Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- FuseSoc Verification Automation☆22Updated 3 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Updated 2 weeks ago
- A padring generator for ASICs☆25Updated 2 years ago
- Example of how to use UVM with Verilator☆27Updated last month
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆36Updated 7 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- D3.js based wave (signal) visualizer☆67Updated 3 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- sample VCD files☆39Updated 2 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- OpenFPGA☆34Updated 7 years ago
- Cross EDA Abstraction and Automation☆40Updated 2 weeks ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- Provides automation scripts for building BFMs☆16Updated 7 months ago