Alternatives and similar repositories for kratos

Users that are interested in kratos are comparing it to the libraries listed below

• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• rdaly525 / coreir
  ☆104Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 9 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated this week
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆47Updated last year
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• phanrahan / mantle
  mantle library
  ☆44Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆26Updated last month
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 8 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆23Updated last week
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated last week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago