Kuree / kratosLinks
Debuggable hardware generator
☆69Updated 2 years ago
Alternatives and similar repositories for kratos
Users that are interested in kratos are comparing it to the libraries listed below
Sorting:
- Hardware generator debugger☆75Updated last year
- ☆103Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆85Updated 2 weeks ago
- mantle library☆44Updated 2 years ago
- ☆38Updated 3 years ago
- A SystemVerilog source file pickler.☆59Updated 10 months ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- An automatic clock gating utility☆50Updated 4 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated last month
- ☆56Updated 3 years ago
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- Fast PnR toolchain for CGRA☆18Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 10 months ago
- Next generation CGRA generator☆113Updated 3 weeks ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆32Updated 7 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆39Updated 4 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆110Updated 3 months ago
- A configurable SRAM generator☆53Updated this week
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Visual Simulation of Register Transfer Logic☆100Updated this week
- ☆79Updated last year