Alternatives and similar repositories for dahlia

Users that are interested in dahlia are comparing it to the libraries listed below

• vegaluisjose / reticle
  ☆40Updated 4 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆170Updated last month
• rdaly525 / coreir
  ☆104Updated 3 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆97Updated last month
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated this week
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆54Updated last month
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆57Updated 5 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 6 years ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆265Updated 6 months ago
• David-Durst / embeddedHaskellAetherling
  ☆30Updated 3 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆164Updated 2 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆155Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆38Updated 2 weeks ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• BSVLang / Main
  Main page
  ☆129Updated 5 years ago
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆160Updated this week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆120Updated 8 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆13Updated 4 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated last week
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆111Updated 9 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated 2 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆231Updated this week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 2 weeks ago
• microsoft / kanagawa
  High level synthesis language for hardware design
  ☆80Updated last month