Alternatives and similar repositories for dahlia

Users that are interested in dahlia are comparing it to the libraries listed below

• vegaluisjose / reticle
  ☆40Updated 3 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆159Updated last month
• rdaly525 / coreir
  ☆103Updated 3 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆55Updated 2 weeks ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆92Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated 3 weeks ago
• David-Durst / embeddedHaskellAetherling
  ☆26Updated 2 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆262Updated last month
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆78Updated last year
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆157Updated 2 weeks ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆51Updated 3 weeks ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated this week
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆61Updated 3 weeks ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆34Updated 3 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• CTSRD-CHERI / bluecheck
  A generic test bench written in Bluespec
  ☆54Updated 4 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated 2 months ago
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆542Updated this week
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 11 months ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆106Updated 9 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆124Updated this week
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆23Updated 4 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆109Updated 2 months ago