cucapra / dahlia
Time-sensitive affine types for predictable hardware generation
☆142Updated 8 months ago
Alternatives and similar repositories for dahlia:
Users that are interested in dahlia are comparing it to the libraries listed below
- A core language for rule-based hardware design 🦑☆148Updated 6 months ago
- ☆40Updated 3 years ago
- ☆102Updated 2 years ago
- high-performance RTL simulator☆156Updated 9 months ago
- A Hardware Pipeline Description Language☆43Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆100Updated 5 years ago
- Chisel/Firrtl execution engine☆154Updated 7 months ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆525Updated this week
- A Modeling and Verification Platform for SoCs using ILAs☆75Updated 9 months ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆90Updated 9 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆105Updated this week
- A hardware compiler based on LLHD and CIRCT☆256Updated last year
- The source code to the Voss II Hardware Verification Suite☆56Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆250Updated last month
- ☆25Updated 2 years ago
- A generic test bench written in Bluespec☆51Updated 4 years ago
- ILA Model Database☆22Updated 4 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- Bluespec BSV HLHDL tutorial☆103Updated 9 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆151Updated 6 months ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆71Updated 7 months ago
- Fearless hardware design☆175Updated this week
- simple snapshot-style integration testing for commands☆70Updated 9 months ago
- A formal semantics of the RISC-V ISA in Haskell☆163Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆91Updated this week
- The specification for the FIRRTL language☆53Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆173Updated 8 months ago
- CoreIR Symbolic Analyzer☆70Updated 4 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated last month
- Languages, Tools, and Techniques for Accelerator Design☆32Updated 3 years ago