cristian-mattarei / CoSA
CoreIR Symbolic Analyzer
☆72Updated 4 years ago
Alternatives and similar repositories for CoSA:
Users that are interested in CoSA are comparing it to the libraries listed below
- Hardware Formal Verification Tool☆48Updated this week
- The HW-CBMC and EBMC Model Checkers for Verilog☆67Updated this week
- A Modeling and Verification Platform for SoCs using ILAs☆76Updated 10 months ago
- Reads a state transition system and performs property checking☆79Updated 2 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆21Updated 3 months ago
- The source code to the Voss II Hardware Verification Suite☆56Updated 2 weeks ago
- Collection for submission (Hardware Model Checking Benchmark)☆9Updated 6 months ago
- BTOR2 MLIR project☆25Updated last year
- AIGER And-Inverter-Graph Library☆74Updated 3 weeks ago
- Pono: A flexible and extensible SMT-based model checker☆101Updated this week
- ILA Model Database☆22Updated 4 years ago
- ☆13Updated 4 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆14Updated 2 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆15Updated 6 years ago
- A generic parser and tool package for the BTOR2 format.☆41Updated 4 months ago
- Equivalence checking with Yosys☆42Updated 3 weeks ago
- ☆12Updated 2 years ago
- ☆102Updated 2 years ago
- Fast Symbolic Repair of Hardware Design Code☆22Updated 3 months ago
- A Hardware Pipeline Description Language☆44Updated last year
- ☆23Updated 4 years ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆11Updated 7 months ago
- Verilog development and verification project for HOL4☆26Updated last week
- A Formal Verification Framework for Chisel☆18Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆13Updated last month
- ☆12Updated 4 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆29Updated 9 months ago
- ☆18Updated 10 months ago
- ☆19Updated 9 months ago