cristian-mattarei / CoSALinks
CoreIR Symbolic Analyzer
☆72Updated 4 years ago
Alternatives and similar repositories for CoSA
Users that are interested in CoSA are comparing it to the libraries listed below
Sorting:
- Hardware Formal Verification Tool☆52Updated this week
- The HW-CBMC and EBMC Model Checkers for Verilog☆72Updated this week
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated 10 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- ILA Model Database☆22Updated 4 years ago
- Reads a state transition system and performs property checking☆81Updated 3 months ago
- Pono: A flexible and extensible SMT-based model checker☆102Updated this week
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 7 months ago
- AIGER And-Inverter-Graph Library☆78Updated last week
- LLM Evaluation Benchmark on Hardware Formal Verification☆21Updated last month
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆15Updated 6 years ago
- A generic parser and tool package for the BTOR2 format.☆41Updated 3 weeks ago
- Equivalence checking with Yosys☆43Updated 3 weeks ago
- Fast Symbolic Repair of Hardware Design Code☆23Updated 4 months ago
- BTOR2 MLIR project☆25Updated last year
- A tool for checking the contract satisfaction for hardware designs☆11Updated 6 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆14Updated 2 years ago
- ☆13Updated 4 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last month
- ☆12Updated 2 years ago
- ☆103Updated 2 years ago
- A Formal Verification Framework for Chisel☆18Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆33Updated 3 years ago
- Recent papers related to hardware formal verification.☆70Updated last year
- Project Repo for the Simulator Independent Coverage Research☆19Updated 2 years ago
- ☆15Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆32Updated 10 months ago
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 5 years ago
- Source files to reproduce the results shown for A-QED at DAC 2020☆9Updated 4 years ago