Alternatives and similar repositories for CoSA

Users that are interested in CoSA are comparing it to the libraries listed below

• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆99Updated this week
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆76Updated this week
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆117Updated 2 weeks ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆45Updated 3 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆53Updated 2 weeks ago
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆88Updated 3 months ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆11Updated last month
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated 3 weeks ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 5 months ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• iscas-tis / CHA
  ☆19Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆34Updated 8 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆32Updated 11 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆94Updated 4 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 years ago
• efeslab / hardware-bugbase
  ☆20Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• sterin / super-prove-build
  ☆14Updated 5 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated 3 weeks ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 7 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago