cristian-mattarei / CoSA
CoreIR Symbolic Analyzer
☆63Updated 4 years ago
Alternatives and similar repositories for CoSA:
Users that are interested in CoSA are comparing it to the libraries listed below
- The HW-CBMC and EBMC Model Checkers for Verilog☆63Updated this week
- Reads a state transition system and performs property checking☆76Updated 3 months ago
- Hardware Model Checker☆30Updated last week
- A Modeling and Verification Platform for SoCs using ILAs☆75Updated 7 months ago
- Pono: A flexible and extensible SMT-based model checker☆89Updated this week
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆13Updated 2 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆18Updated last month
- A generic parser and tool package for the BTOR2 format.☆41Updated 2 months ago
- ILA Model Database☆22Updated 4 years ago
- AIGER And-Inverter-Graph Library☆67Updated last month
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- Fast Symbolic Repair of Hardware Design Code☆21Updated 3 weeks ago
- Integer Multiplier Generator for Verilog☆20Updated last year
- ☆13Updated 4 years ago
- BTOR2 MLIR project☆23Updated last year
- The source code to the Voss II Hardware Verification Suite☆53Updated last week
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- An advanced header-only exact synthesis library☆24Updated 2 years ago
- ☆102Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 6 months ago
- A Hardware Pipeline Description Language☆44Updated last year
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 5 months ago
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated last year
- Equivalence checking with Yosys☆40Updated this week
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- ☆12Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago