Alternatives and similar repositories for livehd

Users that are interested in livehd are comparing it to the libraries listed below

• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆171Updated 2 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆309Updated 3 months ago
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆116Updated 3 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆223Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated last week
• rdaly525 / coreir
  ☆104Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆434Updated 4 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆352Updated this week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆121Updated this week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆221Updated 3 weeks ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated this week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• lsils / mockturtle
  C++ logic network library
  ☆273Updated 3 months ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 2 months ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated 2 weeks ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆249Updated 3 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆354Updated this week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 8 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year