Alternatives and similar repositories for livehd

Users that are interested in livehd are comparing it to the libraries listed below

• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆249Updated 5 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆310Updated last week
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆174Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated last month
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆442Updated 5 months ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated last month
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆355Updated this week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆186Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆227Updated 11 months ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆124Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆196Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆357Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆271Updated 3 weeks ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆63Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆184Updated 9 months ago
• lsils / mockturtle
  C++ logic network library
  ☆275Updated 4 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated last month
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆211Updated last year
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆300Updated 3 weeks ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆244Updated this week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆135Updated 6 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆116Updated last week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 3 months ago
• hlslibs / ac_types
  Algorithmic C Datatypes
  ☆134Updated last month
• ferrandi / PandA-bambu
  PandA-bambu public repository
  ☆313Updated 3 weeks ago