Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
☆237May 21, 2026Updated this week
Alternatives and similar repositories for livehd
Users that are interested in livehd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- magma circuits☆265Oct 19, 2024Updated last year
- IDEA project source files☆112Apr 15, 2026Updated last month
- ☆105Jun 27, 2022Updated 3 years ago
- C++ logic network library☆293May 11, 2026Updated 2 weeks ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆121Apr 1, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- SystemVerilog compiler and language services☆1,039May 16, 2026Updated last week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆453Apr 5, 2026Updated last month
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆325Jun 30, 2025Updated 10 months ago
- ☆15Oct 24, 2019Updated 6 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- An advanced header-only exact synthesis library☆31Nov 24, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- Build Customized FPGA Implementations for Vivado☆375May 16, 2026Updated last week
- Database and Tool Framework for EDA☆125Jan 25, 2021Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆460Updated this week
- ☆30Oct 16, 2022Updated 3 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225Updated this week
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- Showcase examples for EPFL logic synthesis libraries☆206Apr 5, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- DATC Robust Design Flow.☆36Jan 21, 2020Updated 6 years ago
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated 10 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- A circuit toolkit☆108Feb 23, 2020Updated 6 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆255May 8, 2026Updated 2 weeks ago
- D3.js and ELK based schematic visualizer☆119May 13, 2026Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆318Mar 6, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Test suite designed to check compliance with the SystemVerilog standard.☆375Updated this week
- Modular hardware build system☆1,158May 19, 2026Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆292May 9, 2026Updated 2 weeks ago
- Object-Oriented Programming☆12Aug 26, 2021Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 10 months ago
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆114Apr 27, 2026Updated 3 weeks ago
- Circuit IR Compilers and Tools☆2,129May 19, 2026Updated last week