masc-ucsc / livehdLinks
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
☆223Updated this week
Alternatives and similar repositories for livehd
Users that are interested in livehd are comparing it to the libraries listed below
Sorting:
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆219Updated last week
- Build Customized FPGA Implementations for Vivado☆327Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆261Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆282Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆395Updated last week
- magma circuits☆261Updated 8 months ago
- ☆103Updated 2 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆328Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 7 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆159Updated 2 weeks ago
- high-performance RTL simulator☆160Updated last year
- SystemRDL 2.0 language compiler front-end☆254Updated 3 months ago
- SystemVerilog synthesis tool☆198Updated 3 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆122Updated 3 weeks ago
- SystemVerilog frontend for Yosys☆128Updated this week
- A complete open-source design-for-testing (DFT) Solution☆159Updated 3 weeks ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆277Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆457Updated last week
- Next generation CGRA generator☆112Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 4 years ago
- ACT hardware description language and core tools.☆112Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆581Updated 2 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- A dependency management tool for hardware projects.☆307Updated last month
- Fabric generator and CAD tools.☆187Updated last week
- Main page☆126Updated 5 years ago
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆133Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month