masc-ucsc / livehdLinks
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
☆227Updated this week
Alternatives and similar repositories for livehd
Users that are interested in livehd are comparing it to the libraries listed below
Sorting:
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆162Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆224Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆285Updated 2 months ago
- magma circuits☆261Updated 9 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- ☆103Updated 3 years ago
- Build Customized FPGA Implementations for Vivado☆330Updated this week
- high-performance RTL simulator☆168Updated last year
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆281Updated 3 weeks ago
- C++ logic network library☆243Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆403Updated this week
- Next generation CGRA generator☆112Updated this week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆215Updated 3 weeks ago
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- SystemVerilog synthesis tool☆206Updated 4 months ago
- SystemVerilog frontend for Yosys☆148Updated last week
- Open-source FPGA research and prototyping framework.☆208Updated 11 months ago
- FPGA tool performance profiling☆102Updated last year
- ACT hardware description language and core tools.☆117Updated this week
- PandA-bambu public repository☆273Updated last month
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆134Updated 6 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- IDEA project source files☆107Updated 8 months ago
- Fabric generator and CAD tools.☆192Updated last week
- ☆86Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago