Veriloggen: A Mixed-Paradigm Hardware Construction Framework
☆327Mar 8, 2026Updated 7 months ago
Alternatives and similar repositories for veriloggen
Users that are interested in veriloggen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆367Oct 17, 2023Updated 3 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆54Nov 21, 2016Updated 9 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- ☆43May 26, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Oct 16, 2026Updated 2 weeks ago
- magma circuits☆264Oct 19, 2024Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆110Apr 14, 2026Updated 6 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆470Sep 10, 2026Updated last month
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 11 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Oct 7, 2026Updated 3 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- The MyHDL development repository☆1,131Sep 14, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆476Updated this week
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆306Updated this week
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆109Jan 29, 2022Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆252Updated this week
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Code generation tool for control and status registers☆474Sep 11, 2026Updated last month
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆300Jun 18, 2026Updated 4 months ago
- Hardware Description Languages☆1,184Jul 9, 2026Updated 3 months ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- SystemVerilog to Verilog conversion☆758Aug 18, 2026Updated 2 months ago
- HW Design: A Functional Approach☆146Jun 26, 2023Updated 3 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated last month
- An open-source static random access memory (SRAM) compiler.☆1,169Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 11 years ago
- cocotb: Python-based chip (RTL) verification☆2,558Updated this week
- Connecting SystemC with SystemVerilog☆43Mar 25, 2012Updated 14 years ago
- Network on Chip Implementation written in SytemVerilog☆215Aug 27, 2022Updated 4 years ago
- Yosys Open SYnthesis Suite☆4,855Updated this week
- Running Python code in SystemVerilog☆73May 8, 2026Updated 5 months ago