Veriloggen: A Mixed-Paradigm Hardware Construction Framework
☆325Mar 8, 2026Updated 3 months ago
Alternatives and similar repositories for veriloggen
Users that are interested in veriloggen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆796Jun 15, 2024Updated last year
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆366Oct 17, 2023Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆23Nov 25, 2018Updated 7 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆53Nov 21, 2016Updated 9 years ago
- ☆43May 26, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 19, 2026Updated 3 weeks ago
- Polyphony is Python based High-Level Synthesis compiler.☆110Apr 14, 2026Updated last month
- magma circuits☆265Oct 19, 2024Updated last year
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆455Apr 5, 2026Updated 2 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- The MyHDL development repository☆1,119Apr 10, 2025Updated last year
- The Shang high-level synthesis framework☆120May 29, 2014Updated 12 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆258May 31, 2026Updated last week
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆301May 28, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463May 31, 2026Updated last week
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated 4 months ago
- Hardware Description Languages☆1,151Apr 6, 2026Updated 2 months ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- Code generation tool for control and status registers☆463May 30, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,513Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆238Updated this week
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- An open-source static random access memory (SRAM) compiler.☆1,069May 15, 2026Updated 3 weeks ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆109Jan 29, 2022Updated 4 years ago
- SystemVerilog to Verilog conversion☆734Mar 28, 2026Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆293May 9, 2026Updated last month
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 6 years ago
- few python scripts to clone all IP cores from opencores.org☆28Jan 8, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 6 months ago
- Icarus Verilog☆3,478Jun 1, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆472Mar 30, 2026Updated 2 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,854Mar 13, 2026Updated 2 months ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆29May 28, 2026Updated 2 weeks ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆208Aug 27, 2022Updated 3 years ago