Alternatives and similar repositories for veriloggen:

Users that are interested in veriloggen are comparing it to the libraries listed below

• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆707Updated 10 months ago
• NNgen / nngen
  NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
  ☆351Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆381Updated 2 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆354Updated 7 years ago
• phanrahan / magma
  magma circuits
  ☆260Updated 6 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆291Updated 2 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆423Updated 3 weeks ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆251Updated 3 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆439Updated 2 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆256Updated last year
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆104Updated 3 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆409Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆614Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆684Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆211Updated 5 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆552Updated 3 weeks ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆315Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 2 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆132Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 6 months ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆239Updated 5 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆249Updated 2 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆621Updated last month
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆421Updated last month
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆628Updated 2 years ago