PyHDI / veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
☆313Updated 8 months ago
Alternatives and similar repositories for veriloggen:
Users that are interested in veriloggen are comparing it to the libraries listed below
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆700Updated 10 months ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆350Updated 7 years ago
- magma circuits☆259Updated 6 months ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆349Updated last year
- SystemRDL 2.0 language compiler front-end☆250Updated last month
- Code generation tool for control and status registers☆380Updated 2 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆291Updated last month
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆433Updated last month
- Polyphony is Python based High-Level Synthesis compiler.☆103Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆475Updated 2 months ago
- Network on Chip Implementation written in SytemVerilog☆172Updated 2 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆210Updated 4 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆567Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆409Updated last month
- Common SystemVerilog components☆601Updated this week
- UVM 1.2 port to Python☆250Updated 2 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆418Updated last month
- AXI interface modules for Cocotb☆252Updated last year
- The UVM written in Python☆422Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆247Updated last month
- Support for Rocket Chip on Zynq FPGAs☆407Updated 6 years ago
- Bus bridges and other odds and ends☆542Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆388Updated this week
- Build Customized FPGA Implementations for Vivado☆313Updated this week
- SystemVerilog to Verilog conversion☆615Updated last week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆199Updated 5 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆313Updated this week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆129Updated last year
- Python-based hardware modeling framework☆239Updated 5 years ago
- ☆198Updated last month