PyHDI / veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
☆312Updated 7 months ago
Alternatives and similar repositories for veriloggen:
Users that are interested in veriloggen are comparing it to the libraries listed below
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆690Updated 9 months ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆349Updated last year
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆344Updated 7 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆289Updated 2 weeks ago
- magma circuits☆259Updated 5 months ago
- Code generation tool for control and status registers☆375Updated last month
- SystemRDL 2.0 language compiler front-end☆249Updated 2 weeks ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆208Updated 4 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- Python-based hardware modeling framework☆239Updated 5 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆429Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆103Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆309Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated last week
- Common SystemVerilog components☆593Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆560Updated this week
- The UVM written in Python☆415Updated 2 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆246Updated last month
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆407Updated 2 weeks ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆265Updated 4 months ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆127Updated last year
- HW Design: A Functional Approach☆145Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆383Updated this week
- UVM 1.2 port to Python☆250Updated last month
- Bus bridges and other odds and ends☆526Updated last month
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 6 months ago
- AXI interface modules for Cocotb☆245Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆410Updated last week