Alternatives and similar repositories for fpu_div_sqrt_mvp

Users that are interested in fpu_div_sqrt_mvp are comparing it to the libraries listed below

• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆53Updated last year
• pulp-platform / fpu
  ☆51Updated 6 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆42Updated last year
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆28Updated 7 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆58Updated this week
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆56Updated 2 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated 2 months ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆74Updated 7 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 6 months ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆49Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 4 years ago
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆13Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated this week
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆58Updated last year
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆14Updated 6 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆50Updated 3 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆29Updated 6 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆73Updated 4 years ago
• prasadp4009 / 2-way-Set-Associative-Cache-Controller
  Synthesizable and Parameterized Cache Controller in Verilog
  ☆44Updated 2 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆44Updated last year
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago