[UNRELEASED] FP div/sqrt unit for transprecision
☆27Sep 9, 2025Updated 6 months ago
Alternatives and similar repositories for fpu_div_sqrt_mvp
Users that are interested in fpu_div_sqrt_mvp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆59Feb 18, 2019Updated 7 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- ☆11Feb 16, 2019Updated 7 years ago
- ☆14Feb 24, 2025Updated last year
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆577Mar 11, 2026Updated last week
- ☆10Feb 27, 2020Updated 6 years ago
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- Open IP in Hardware Description Language.☆30Sep 4, 2023Updated 2 years ago
- ☆13Jan 14, 2021Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- ☆23Mar 15, 2025Updated last year
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Mar 14, 2026Updated last week
- Direct Access Memory for MPSoC☆13Feb 28, 2026Updated 3 weeks ago
- Hardware Description Language Translator☆17Feb 28, 2026Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- Basic floating-point components for RISC-V processors☆68Dec 4, 2019Updated 6 years ago
- ☆23Oct 8, 2019Updated 6 years ago
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- ☆22Feb 22, 2020Updated 6 years ago
- Simple single-port AXI memory interface☆49Jun 7, 2024Updated last year
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Updated this week
- ☆16May 10, 2019Updated 6 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated last month
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆44May 26, 2021Updated 4 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Mar 11, 2026Updated last week
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆19Aug 30, 2020Updated 5 years ago