An open-source static random access memory (SRAM) compiler.
☆1,136Aug 16, 2026Updated last month
Alternatives and similar repositories for OpenRAM
Users that are interested in OpenRAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,939Mar 25, 2026Updated 5 months ago
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,713Jul 21, 2026Updated last month
- Magic VLSI Layout Tool☆704Updated this week
- AMC: Asynchronous Memory Compiler☆56Jun 29, 2020Updated 6 years ago
- Modular hardware build system☆1,215Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆3,111Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆453Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆296Jun 18, 2026Updated 3 months ago
- An Open-source FPGA IP Generator☆1,152Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆827Updated this week
- SystemVerilog to Verilog conversion☆753Aug 18, 2026Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆175Nov 10, 2025Updated 10 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆357Oct 22, 2025Updated 10 months ago
- Yosys Open SYnthesis Suite☆4,759Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- BaseJump STL: A Standard Template Library for SystemVerilog☆681Sep 8, 2026Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆236Oct 26, 2024Updated last year
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆138Feb 22, 2022Updated 4 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆325Aug 7, 2026Updated last month
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆373Dec 2, 2025Updated 9 months ago
- An abstraction library for interfacing EDA tools☆794Updated this week
- ☆391Updated this week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆745Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,461Sep 12, 2026Updated last week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- SERV - The SErial RISC-V CPU☆1,886Aug 25, 2026Updated 3 weeks ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆493Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆412Feb 26, 2025Updated last year
- Common SystemVerilog components☆799Updated this week
- OpenSTA engine☆619Updated this week
- https://caravel-user-project.readthedocs.io☆239Feb 25, 2025Updated last year
- sram/rram/mram.. compiler☆56Sep 11, 2023Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆91May 2, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Updated this week
- A Linux-capable RISC-V multicore for and by the world☆832Updated this week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆246Mar 8, 2020Updated 6 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆716Dec 26, 2025Updated 8 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,267Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,062Updated this week