openhwgroup / cv32e40x-dv
CV32E40X Design-Verification environment
☆11Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for cv32e40x-dv
- The multi-core cluster of a PULP system.☆56Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆32Updated 2 weeks ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 4 months ago
- ☆33Updated this week
- ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆25Updated this week
- Wrappers for open source FPU hardware implementations.☆31Updated 7 months ago
- Simple runtime for Pulp platforms☆34Updated last week
- A Rocket-based RISC-V superscalar in-order core☆27Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Updated last year
- DUTH RISC-V Superscalar Microprocessor☆28Updated 2 weeks ago
- Original RISC-V 1.0 implementation. Not supported.☆40Updated 6 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Intel Compiler for SystemC☆23Updated last year
- ☆20Updated last month
- Verilog behavioral description of various memories☆30Updated 2 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆24Updated last year
- ☆14Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 2 weeks ago
- RISC-V Nexus Trace TG documentation and reference code☆43Updated last month
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Pulp virtual platform☆21Updated 2 years ago
- ☆40Updated 5 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆18Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆32Updated 9 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆26Updated this week
- ☆21Updated 7 years ago
- ☆34Updated this week
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year