openhwgroup / cve2Links
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
☆48Updated 2 weeks ago
Alternatives and similar repositories for cve2
Users that are interested in cve2 are comparing it to the libraries listed below
Sorting:
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- RISC-V Verification Interface☆107Updated 3 weeks ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated 2 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆144Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- RISC-V Nox core☆68Updated 2 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆113Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- Generic Register Interface (contains various adapters)☆130Updated last week
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- Open source ISS and logic RISC-V 32 bit project☆61Updated 3 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- ☆99Updated 2 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆90Updated 4 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆52Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆115Updated 4 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- The multi-core cluster of a PULP system.☆108Updated 2 weeks ago
- RISC-V microcontroller IP core developed in Verilog☆183Updated last week
- Platform Level Interrupt Controller☆43Updated last year
- pulp_soc is the core building component of PULP based SoCs☆80Updated 7 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- Arduino compatible Risc-V Based SOC☆156Updated last year