pulp-platform / fpu_ssLinks
CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
☆13Updated 2 months ago
Alternatives and similar repositories for fpu_ss
Users that are interested in fpu_ss are comparing it to the libraries listed below
Sorting:
- ☆40Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- A verilog implementation for Network-on-Chip☆81Updated 8 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Updated 3 months ago
- Two Level Cache Controller implementation in Verilog HDL☆57Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- ☆58Updated 6 years ago
- ☆29Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Simple single-port AXI memory interface☆49Updated last year
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Advanced Architecture Labs with CVA6☆76Updated 2 years ago
- ☆70Updated 3 years ago
- ☆31Updated 5 years ago
- Public release☆58Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆46Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆17Updated 9 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago