pulp-platform / fpu_ssLinks
CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
☆11Updated 3 weeks ago
Alternatives and similar repositories for fpu_ss
Users that are interested in fpu_ss are comparing it to the libraries listed below
Sorting:
- ☆34Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- ☆53Updated 6 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆23Updated last year
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- Advanced Architecture Labs with CVA6☆66Updated last year
- ☆14Updated last year
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆16Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆74Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 11 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year