Alternatives and similar repositories for Hazard3:

Users that are interested in Hazard3 are comparing it to the libraries listed below

• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,519Updated 2 weeks ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆622Updated last week
• YosysHQ / apicula
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs
  ☆544Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,004Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,298Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,715Updated this week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆642Updated last week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,664Updated last month
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,413Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆402Updated 2 months ago
• lawrie / fpga_pio
  An attempt to recreate the RP2040 PIO in an FPGA
  ☆296Updated 9 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,507Updated last week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆329Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆379Updated 2 months ago
• litex-hub / litex-boards
  LiteX boards files
  ☆397Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆671Updated last month
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆479Updated last month
• splinedrive / kianRiscV
  RISC-V Linux SoC, marchID: 0x2b
  ☆808Updated 2 weeks ago
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆499Updated 7 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆634Updated 2 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,709Updated last month
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆403Updated 2 years ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆421Updated 6 months ago
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆668Updated 3 years ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,257Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,033Updated last month
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆295Updated 3 years ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,045Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆249Updated last month