3-stage RV32IMACZb* processor with debug
☆1,038Apr 16, 2026Updated this week
Alternatives and similar repositories for Hazard3
Users that are interested in Hazard3 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆199Jul 29, 2025Updated 8 months ago
- SERV - The SErial RISC-V CPU☆1,785Feb 19, 2026Updated 2 months ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆38Jul 1, 2023Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆114Updated this week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,038Apr 13, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An attempt to recreate the RP2040 PIO in an FPGA☆315Jun 6, 2024Updated last year
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆93Apr 10, 2026Updated last week
- Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink☆299Dec 14, 2025Updated 4 months ago
- RISC-V XV6/Linux SoC, marchID: 0x2b☆1,077Mar 3, 2026Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,118Feb 11, 2026Updated 2 months ago
- Build your hardware, easily!☆3,835Apr 8, 2026Updated last week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆188Mar 10, 2024Updated 2 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,107Jun 27, 2024Updated last year
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,470Nov 18, 2025Updated 5 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆518Updated this week
- Opensource DDR3 Controller☆427Jan 18, 2026Updated 3 months ago
- A Linux-capable RISC-V multicore for and by the world☆794Apr 8, 2026Updated last week
- Reusable Verilog 2005 components for FPGA designs☆51Dec 14, 2025Updated 4 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆978Nov 15, 2024Updated last year
- A modern hardware definition language and toolchain based on Python☆1,987Apr 10, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,402Updated this week
- Universal utility for programming FPGA☆1,595Updated this week
- A tiny C header-only risc-v emulator.☆2,088Dec 21, 2025Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Smol 2-stage RISC-V processor in nMigen☆26May 6, 2021Updated 4 years ago
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆657Updated this week
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated last month
- A Risc-V SoC for Tiny Tapeout☆52Dec 2, 2025Updated 4 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆591Apr 7, 2026Updated 2 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,895Updated this week
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,410Apr 13, 2026Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,443Updated this week
- Bitbanged DVI on the RP2040 Microcontroller☆1,461Aug 8, 2025Updated 8 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,217Updated this week
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated last month
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,235Sep 18, 2021Updated 4 years ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆225Feb 19, 2026Updated 2 months ago
- nextpnr portable FPGA place and route tool☆1,650Updated this week
- Linux capable RISC-V SoC designed to be readable and useful.☆160Dec 19, 2025Updated 4 months ago