Wren6991 / Hazard3
3-stage RV32IMACZb* processor with debug
☆715Updated last month
Related projects ⓘ
Alternatives and complementary repositories for Hazard3
- SERV - The SErial RISC-V CPU☆1,442Updated last week
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆493Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆856Updated this week
- A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …☆1,597Updated last week
- RISC-V Linux SoC, marchID: 0x2b☆711Updated this week
- Linux on LiteX-VexRiscv☆588Updated 4 months ago
- Universal utility for programming FPGA☆1,218Updated last week
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆602Updated this week
- An attempt to recreate the RP2040 PIO in an FPGA☆292Updated 5 months ago
- ECP5 breakout board in a feather physical format☆491Updated 2 weeks ago
- Small footprint and configurable DRAM core☆382Updated last month
- A modern hardware definition language and toolchain based on Python☆1,576Updated this week
- PCB for ULX3S FPGA R&D board☆377Updated last year
- LiteX boards files☆379Updated this week
- FOSS Flow For FPGA☆361Updated last month
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆587Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆626Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆271Updated this week
- nextpnr portable FPGA place and route tool☆1,314Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆865Updated 3 years ago
- Example designs showing different ways to use F4PGA toolchains.☆267Updated 7 months ago
- Multi-platform nightly builds of open source FPGA tools☆290Updated 3 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,205Updated 2 weeks ago
- VRoom! RISC-V CPU☆480Updated 2 months ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,002Updated 3 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆624Updated this week
- Small footprint and configurable PCIe core☆482Updated last month
- ☆516Updated last week
- CORE-V Family of RISC-V Cores☆206Updated 9 months ago
- An open source USB bootloader for FPGAs☆356Updated last year