OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
☆1,726Sep 15, 2025Updated 6 months ago
Alternatives and similar repositories for OpenLane
Users that are interested in OpenLane are comparing it to the libraries listed below
Sorting:
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,450Oct 28, 2024Updated last year
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,507Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆335Dec 2, 2025Updated 3 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆402Mar 5, 2026Updated 2 weeks ago
- An open-source static random access memory (SRAM) compiler.☆1,021Mar 12, 2026Updated last week
- OpenSTA engine☆555Updated this week
- Magic VLSI Layout Tool☆621Updated this week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆590Mar 14, 2026Updated last week
- Modular hardware build system☆1,131Updated this week
- Yosys Open SYnthesis Suite☆4,333Updated this week
- An Open-source FPGA IP Generator☆1,058Mar 13, 2026Updated last week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Feb 22, 2022Updated 4 years ago
- https://caravel-user-project.readthedocs.io☆230Feb 25, 2025Updated last year
- Fully Open Source FASOC generators built on top of open-source EDA tools☆323Oct 22, 2025Updated 4 months ago
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆694Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆473May 31, 2023Updated 2 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆387Feb 26, 2025Updated last year
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆448Mar 12, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆800Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,797Feb 17, 2026Updated last month
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆161Jun 1, 2024Updated last year
- Qflow full end-to-end digital synthesis flow for ASIC designs☆228Oct 26, 2024Updated last year
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,213Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,789Mar 13, 2026Updated last week
- cocotb: Python-based chip (RTL) verification☆2,284Mar 13, 2026Updated last week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆130Feb 3, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,766Feb 19, 2026Updated last month
- SystemVerilog to Verilog conversion☆709Nov 24, 2025Updated 3 months ago
- A complete open-source design-for-testing (DFT) Solution☆182Aug 30, 2025Updated 6 months ago
- ☆385Apr 13, 2023Updated 2 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆691Dec 26, 2025Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆451Mar 8, 2026Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆3,439Updated this week
- Build your hardware, easily!☆3,773Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,024Jun 27, 2024Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆108Aug 21, 2024Updated last year
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,132Mar 11, 2026Updated last week