The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
☆1,470Updated 2 months ago
Alternatives and similar repositories for OpenLane:
Users that are interested in OpenLane are comparing it to the libraries listed below
- An open-source static random access memory (SRAM) compiler.☆891Updated 3 weeks ago
- An Open-source FPGA IP Generator☆901Updated this week
- Magic VLSI Layout Tool☆529Updated 2 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,822Updated this week
- cocotb: Python-based chip (RTL) verification☆1,962Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆520Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,271Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,025Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,520Updated this week
- Modular hardware build system☆979Updated this week
- nextpnr portable FPGA place and route tool☆1,421Updated this week
- SystemVerilog to Verilog conversion☆616Updated 2 weeks ago
- An abstraction library for interfacing EDA tools☆684Updated 2 weeks ago
- VeeR EH1 core☆872Updated last year
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,524Updated this week
- SERV - The SErial RISC-V CPU☆1,564Updated last month
- OpenSTA engine☆456Updated last week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,082Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,256Updated 2 weeks ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆608Updated 3 weeks ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆1,888Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆393Updated last year
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆637Updated 3 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆322Updated 2 months ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆409Updated this week
- Random instruction generator for RISC-V processor verification☆1,103Updated 2 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆281Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆682Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆908Updated 5 months ago
- lowRISC Style Guides☆422Updated 7 months ago