Alternatives and similar repositories for OpenLane:

Users that are interested in OpenLane are comparing it to the libraries listed below

• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆877Updated 4 months ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆940Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆978Updated this week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆515Updated 2 weeks ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆880Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,487Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,502Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆600Updated 2 weeks ago
• The-OpenROAD-Project / OpenROAD
  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
  ☆1,811Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,400Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,250Updated this week
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
  ☆479Updated this week
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆441Updated 2 weeks ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,061Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,281Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆666Updated last week
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆385Updated this week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆275Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,911Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,023Updated last month
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,485Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆858Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆956Updated 3 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆318Updated 2 weeks ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆786Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆668Updated this week
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆398Updated 2 years ago
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆311Updated last month
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆375Updated 2 months ago
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆385Updated last year