The-OpenROAD-Project / OpenLaneLinks
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
☆1,685Updated 4 months ago
Alternatives and similar repositories for OpenLane
Users that are interested in OpenLane are comparing it to the libraries listed below
Sorting:
- An open-source static random access memory (SRAM) compiler.☆1,000Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,751Updated last week
- Magic VLSI Layout Tool☆609Updated this week
- nextpnr portable FPGA place and route tool☆1,602Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆1,341Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,384Updated last week
- Modular hardware build system☆1,127Updated this week
- An Open-source FPGA IP Generator☆1,044Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,193Updated last week
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆755Updated last week
- cocotb: Python-based chip (RTL) verification☆2,248Updated this week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆557Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆669Updated last week
- OpenSTA engine☆550Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,176Updated 8 months ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,403Updated last week
- An abstraction library for interfacing EDA tools☆748Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆758Updated 3 weeks ago
- VeeR EH1 core☆922Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,176Updated 4 years ago
- SystemVerilog to Verilog conversion☆699Updated 2 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆331Updated 2 months ago
- SERV - The SErial RISC-V CPU☆1,745Updated last month
- The OpenPiton Platform☆763Updated 4 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆377Updated 11 months ago
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆457Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,248Updated 4 months ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,974Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆767Updated last year
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,762Updated last month