Alternatives and similar repositories for learn-fpga:

Users that are interested in learn-fpga are comparing it to the libraries listed below

• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,574Updated last month
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,286Updated last week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,753Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,754Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,465Updated 10 months ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,425Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,042Updated this week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,683Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,862Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,315Updated last week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,395Updated 3 months ago
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,359Updated last month
• splinedrive / kianRiscV
  RISC-V Linux SoC, marchID: 0x2b
  ☆820Updated last week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆639Updated 3 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,792Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,005Updated 3 years ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆981Updated this week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,053Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,530Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,276Updated 2 weeks ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,279Updated last year
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆839Updated this week
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,074Updated 6 months ago
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,771Updated 2 weeks ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,430Updated 3 years ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,455Updated this week
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,072Updated 2 months ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,296Updated last week
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,680Updated last week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆653Updated this week