olofk / corescoreLinks
CoreScore
☆164Updated 2 months ago
Alternatives and similar repositories for corescore
Users that are interested in corescore are comparing it to the libraries listed below
Sorting:
- Example LED blinking project for your FPGA dev board of choice☆185Updated last week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆180Updated last year
- VHDL library 4 FPGAs☆181Updated this week
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- Small footprint and configurable embedded FPGA logic analyzer☆190Updated last week
- Naive Educational RISC V processor☆89Updated last week
- System on Chip toolkit for Amaranth HDL☆95Updated last year
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆83Updated last week
- Project X-Ray Database: XC7 Series☆71Updated 3 years ago
- FuseSoC standard core library☆147Updated 4 months ago
- Board definitions for Amaranth HDL☆120Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- Experimental flows using nextpnr for Xilinx devices☆246Updated last year
- Small footprint and configurable Ethernet core☆265Updated last week
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆140Updated 6 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆90Updated 4 months ago
- Virtual Development Board☆62Updated 3 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- An Open Source configuration of the Arty platform☆133Updated last year
- Ultimate ECP5 development board☆114Updated 6 years ago
- ☆85Updated last week
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- USB Serial on the TinyFPGA BX☆136Updated 4 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆61Updated 5 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆219Updated 3 years ago
- Documenting Lattice's 28nm FPGA parts☆144Updated last year