olofk / corescoreLinks
CoreScore
☆156Updated 4 months ago
Alternatives and similar repositories for corescore
Users that are interested in corescore are comparing it to the libraries listed below
Sorting:
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆172Updated last year
- FuseSoC standard core library☆143Updated 3 weeks ago
- Example LED blinking project for your FPGA dev board of choice☆177Updated 3 weeks ago
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Board definitions for Amaranth HDL☆117Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆240Updated 8 months ago
- System on Chip toolkit for Amaranth HDL☆91Updated 8 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆94Updated last week
- Small footprint and configurable Ethernet core☆247Updated 3 weeks ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- ☆79Updated last year
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆78Updated 3 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- A curated list of awesome resources for HDL design and verification☆151Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆237Updated 7 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- USB Serial on the TinyFPGA BX☆136Updated 4 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆138Updated 2 months ago
- VHDL library 4 FPGAs☆179Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆79Updated this week
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆113Updated 3 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- Verilog wishbone components☆115Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆79Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago