fusesoc / blinkyLinks
Example LED blinking project for your FPGA dev board of choice
☆189Updated last week
Alternatives and similar repositories for blinky
Users that are interested in blinky are comparing it to the libraries listed below
Sorting:
- CoreScore☆171Updated 2 months ago
- VHDL library 4 FPGAs☆185Updated this week
- FuseSoC standard core library☆151Updated last month
- Multi-platform nightly builds of open source FPGA tools☆299Updated 4 years ago
- USB Serial on the TinyFPGA BX☆141Updated 4 years ago
- SoC based on VexRiscv and ICE40 UP5K☆161Updated 10 months ago
- Example designs showing different ways to use F4PGA toolchains.☆282Updated last year
- Experimental flows using nextpnr for Xilinx devices☆252Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆186Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆299Updated this week
- A Video display simulator☆175Updated 8 months ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆219Updated 3 years ago
- Small footprint and configurable Ethernet core☆272Updated this week
- Board definitions for Amaranth HDL☆122Updated 4 months ago
- ☆139Updated this week
- A simple, basic, formally verified UART controller☆321Updated last year
- This repository contains small example designs that can be used with the open source icestorm flow.☆155Updated 4 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 6 months ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated last week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆213Updated last month
- A FPGA core for a simple SDRAM controller.☆122Updated 4 years ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆292Updated last year
- FPGA display controller with support for VGA, DVI, and HDMI.☆244Updated 5 years ago