Alternatives and similar repositories for blinky

Users that are interested in blinky are comparing it to the libraries listed below

• olofk / corescore
  CoreScore
  ☆172Updated 2 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆185Updated this week
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 4 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 10 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆187Updated last year
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆141Updated 4 years ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆283Updated last year
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆273Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆253Updated last year
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆122Updated 5 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated 2 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆301Updated last week
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆155Updated 4 years ago
• ZipCPU / vgasim
  A Video display simulator
  ☆175Updated 8 months ago
• timvideos / litex-buildenv
  An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
  ☆219Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆112Updated last year
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆147Updated 3 weeks ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆74Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated 2 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆323Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated this week
• smunaut / ice40-playground
  Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
  ☆259Updated 2 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆119Updated 4 years ago
• damdoy / ice40_ultraplus_examples
  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
  ☆293Updated last year
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆92Updated 7 months ago