nvdla / docLinks
Documentation for NVDLA.
☆251Updated last month
Alternatives and similar repositories for doc
Users that are interested in doc are comparing it to the libraries listed below
Sorting:
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆145Updated 7 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆163Updated 3 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆230Updated 6 years ago
- NVDLA SW☆503Updated 4 years ago
- Virtual Platform for NVDLA☆150Updated 7 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆308Updated 4 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆231Updated 6 months ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆329Updated 6 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆219Updated 6 years ago
- Getting Started with Xilinx ML Suite☆339Updated 4 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆279Updated 4 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆215Updated 5 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆428Updated 5 years ago
- SDAccel Examples☆358Updated 3 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆262Updated 2 years ago
- A convolutional neural network implemented in hardware (verilog)☆160Updated 7 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆154Updated 5 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆183Updated 8 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- RTL, Cmodel, and testbench for NVDLA☆1,915Updated 3 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆278Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆410Updated 6 years ago
- Xilinx Deep Learning IP☆94Updated 4 years ago
- Network on Chip Simulator☆287Updated last month
- ☆84Updated 5 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆354Updated 7 months ago
- NVDLA Web Content☆44Updated last month
- ☆248Updated 4 years ago
- ☆360Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago