nvdla / doc

Related projects: ⓘ

• OpenDLA / OpenDLA
  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
  ☆138Updated 6 years ago
• JunningWu / Learning-NVDLA-Notes
  NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…
  ☆219Updated 5 years ago
• nvdla / sw
  NVDLA SW
  ☆482Updated 3 years ago
• nvdla / vp
  Virtual Platform for NVDLA
  ☆135Updated 6 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆160Updated 2 years ago
• Xilinx / CHaiDNN
  HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
  ☆320Updated 5 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆199Updated 5 years ago
• nvdla / hw
  RTL, Cmodel, and testbench for NVDLA
  ☆1,712Updated 2 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆206Updated 4 years ago
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆219Updated last week
• Xilinx / SDAccel_Examples
  SDAccel Examples
  ☆354Updated 2 years ago
• cornell-zhang / bnn-fpga
  Binarized Convolutional Neural Networks on Software-Programmable FPGAs
  ☆298Updated 3 years ago
• Xilinx / ml-suite
  Getting Started with Xilinx ML Suite
  ☆335Updated 3 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆253Updated last week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆350Updated this week
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆385Updated 4 years ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆259Updated 4 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆392Updated 5 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆115Updated 5 years ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆777Updated last month
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆169Updated 7 years ago
• Xilinx / HLx_Examples
  ☆298Updated this week
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆212Updated last year
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆149Updated 7 years ago
• ARM-software / SCALE-Sim
  ☆328Updated last year
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
  ☆322Updated 4 months ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆298Updated 2 years ago
• UCSBarchlab / OpenTPU
  A open source reimplementation of Google's Tensor Processing Unit (TPU).
  ☆352Updated 6 years ago
• embedeep / Free-TPU
  Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…
  ☆237Updated last year
• Xilinx / QNN-MO-PYNQ
  ☆236Updated 3 years ago