Documentation for NVDLA.
☆269Mar 26, 2026Updated 4 months ago
Alternatives and similar repositories for doc
Users that are interested in doc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL, Cmodel, and testbench for NVDLA☆2,134Mar 2, 2022Updated 4 years ago
- NVDLA SW☆518Jan 28, 2021Updated 5 years ago
- Virtual Platform for NVDLA☆169Aug 23, 2018Updated 7 years ago
- NVDLA Web Content☆46Mar 26, 2026Updated 4 months ago
- Open Neural Network Compiler☆532Aug 22, 2023Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆232Dec 18, 2018Updated 7 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆146Nov 16, 2017Updated 8 years ago
- OpenDLA for trying the demo and FPGA solution☆17Jul 28, 2022Updated 4 years ago
- umbrella project helps you to build up onnc from scratch☆24Mar 14, 2022Updated 4 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆237Dec 22, 2025Updated 7 months ago
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,111Mar 30, 2026Updated 4 months ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 7 years ago
- OSDT2019相关资料☆16Nov 17, 2019Updated 6 years ago
- armchina NPU parser☆43May 6, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A list of ICs and IPs for AI, Machine Learning and Deep Learning.☆1,713Jul 16, 2026Updated 3 weeks ago
- ☆13Jul 5, 2026Updated last month
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,850Mar 24, 2021Updated 5 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆15Nov 16, 2017Updated 8 years ago
- sgbm ros with cuda☆12Jun 23, 2018Updated 8 years ago
- Rocket Chip Generator☆3,840Jun 2, 2026Updated 2 months ago
- GPGPU microprocessor architecture☆2,213Nov 8, 2024Updated last year
- PolarFire FPGA sample RISC-V designs☆14Oct 15, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VeeR EH1 core☆960Jul 16, 2026Updated 3 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,350Jul 29, 2026Updated last week
- ☆14Jul 16, 2026Updated 3 weeks ago
- CNN accelerator☆30Jun 11, 2017Updated 9 years ago
- An open source GPU based off of the AMD Southern Islands ISA.☆1,401Aug 18, 2025Updated 11 months ago
- A convolutional neural network implemented in hardware (verilog)☆166Sep 7, 2017Updated 8 years ago
- ☆12Jun 11, 2021Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆210Jun 25, 2020Updated 6 years ago
- ☆15Nov 11, 2015Updated 10 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A NVDLA Loadable Parser.☆13Mar 2, 2022Updated 4 years ago
- Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board☆15Nov 16, 2022Updated 3 years ago
- Documentation for the BOOM processor☆47Mar 8, 2017Updated 9 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,060Updated this week
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆25May 8, 2020Updated 6 years ago
- Random instruction generator for RISC-V processor verification☆1,337Apr 3, 2026Updated 4 months ago
- Algorithmic C Math Library☆67Jul 6, 2026Updated last month