nvdla / swLinks
NVDLA SW
☆501Updated 4 years ago
Alternatives and similar repositories for sw
Users that are interested in sw are comparing it to the libraries listed below
Sorting:
- Documentation for NVDLA.☆250Updated last week
- Virtual Platform for NVDLA☆149Updated 6 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆230Updated 6 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆162Updated 3 years ago
- Getting Started with Xilinx ML Suite☆339Updated 4 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 6 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆144Updated 7 years ago
- RTL, Cmodel, and testbench for NVDLA☆1,916Updated 3 years ago
- ☆358Updated 2 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆218Updated 6 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing☆338Updated last year
- An Open Source Deep Learning Inference Engine Based on FPGA☆159Updated 4 years ago
- Open, Modular, Deep Learning Accelerator☆298Updated last year
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆308Updated 4 years ago
- Berkeley's Spatial Array Generator☆1,010Updated 3 months ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆230Updated 6 months ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆225Updated 4 years ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆412Updated 2 weeks ago
- SDAccel Examples☆358Updated 3 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆213Updated 5 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆426Updated 5 years ago
- ☆635Updated 4 years ago
- Run Time for AIE and FPGA based platforms☆611Updated this week
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆221Updated last year
- CSV spreadsheets and other material for AI accelerator survey papers☆173Updated last year
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆261Updated 2 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- Open Neural Network Compiler☆527Updated last year
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆681Updated 7 years ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆643Updated last year