JunningWu / Learning-NVDLA-NotesLinks
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
☆227Updated 6 years ago
Alternatives and similar repositories for Learning-NVDLA-Notes
Users that are interested in Learning-NVDLA-Notes are comparing it to the libraries listed below
Sorting:
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆143Updated 7 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆162Updated 3 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆306Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆155Updated 5 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆186Updated 7 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆229Updated 4 months ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆338Updated last year
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆215Updated 6 years ago
- Documentation for NVDLA.☆248Updated 10 months ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆181Updated 8 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆422Updated 5 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆182Updated last year
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆195Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Virtual Platform for NVDLA☆146Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 6 years ago
- Vitis HLS Library for FINN☆198Updated 3 weeks ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆259Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆102Updated 6 years ago
- FPGA Accelerator for CNN using Vivado HLS☆317Updated 3 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆90Updated 6 years ago
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Updated 7 years ago
- ☆247Updated 4 years ago
- DPU on PYNQ☆222Updated last year
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- Course Webpage for CS 217 Hardware Accelerators for Machine Learning, Stanford University☆97Updated 2 years ago