Alternatives and similar repositories for Elastic-Silicon-Interconnect

Users that are interested in Elastic-Silicon-Interconnect are comparing it to the libraries listed below

• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 8 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆42Updated 3 weeks ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆32Updated 2 months ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆32Updated last month
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• chipsalliance / OmnixtendEndpoint
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
  ☆19Updated 8 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated 2 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated last week
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago