Alternatives and similar repositories for Elastic-Silicon-Interconnect

Users that are interested in Elastic-Silicon-Interconnect are comparing it to the libraries listed below

• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 9 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆91Updated last week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆34Updated 2 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated 3 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆71Updated 2 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆51Updated 3 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆43Updated 3 weeks ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆32Updated 3 months ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆27Updated 2 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week