microsoft / Elastic-Silicon-Interconnect
ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges off-chip and creates high-level APIs using the type data.
☆33Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for Elastic-Silicon-Interconnect
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Hardware generator debugger☆71Updated 9 months ago
- ☆52Updated 2 years ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- A SystemVerilog source file pickler.☆52Updated last month
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆27Updated this week
- ☆22Updated last year
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- Cross EDA Abstraction and Automation☆36Updated this week
- Debuggable hardware generator☆67Updated last year
- An automatic clock gating utility☆43Updated 4 months ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- ☆30Updated last year
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆41Updated 8 months ago
- Benchmarks for Yosys development☆22Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- ☆36Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Useful utilities for BAR projects☆30Updated 10 months ago
- The specification for the FIRRTL language☆46Updated this week
- Source-Opened RISCV for Crypto☆15Updated 2 years ago
- A Verilog Synthesis Regression Test☆34Updated 8 months ago