ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges off-chip and creates high-level APIs using the type data.
☆35Sep 30, 2020Updated 5 years ago
Alternatives and similar repositories for Elastic-Silicon-Interconnect
Users that are interested in Elastic-Silicon-Interconnect are comparing it to the libraries listed below
Sorting:
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- A hardware compiler based on LLHD and CIRCT☆265Jun 30, 2025Updated 8 months ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last week
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- ☆20Mar 1, 2021Updated 5 years ago
- Medium Access Control layer of 802.15.4☆13Nov 14, 2014Updated 11 years ago
- Mutation Cover with Yosys (MCY)☆91Feb 4, 2026Updated last month
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- ☆13Feb 8, 2021Updated 5 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- Intel Compiler for SystemC☆29Jun 1, 2023Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Tools to convert Kicad intermediate netlist to HDL block diagram netlist☆12Jul 21, 2016Updated 9 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- VexRiscv-SMP integration test with LiteX.☆26Nov 16, 2020Updated 5 years ago
- Verilog development and verification project for HOL4☆28Apr 25, 2025Updated 10 months ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- Xilinx Unisim Library in Verilog☆86Jul 22, 2020Updated 5 years ago
- Autonomous Satellite Tracker with ESP8266-Huzzah☆18Jun 8, 2025Updated 8 months ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆313Feb 20, 2026Updated last week
- Languages, Tools, and Techniques for Accelerator Design☆33Nov 2, 2021Updated 4 years ago
- RISC-V port to Parallella Board☆13Aug 22, 2016Updated 9 years ago
- There are many RISC V projects on iCE40. This one is mine.☆14Jun 25, 2020Updated 5 years ago
- ☆11Feb 11, 2019Updated 7 years ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- SPI core☆14Oct 25, 2019Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago