A GPU acceleration flow for RTL simulation with batch stimulus
☆117Apr 1, 2024Updated last year
Alternatives and similar repositories for RTLflow
Users that are interested in RTLflow are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆186Jun 19, 2024Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- ☆14Aug 27, 2020Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆34Apr 13, 2023Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- ☆52Jan 16, 2025Updated last year
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆300Feb 17, 2026Updated 2 weeks ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆140Feb 18, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆450Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆364Updated this week
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- ☆17Oct 7, 2025Updated 5 months ago
- SpiceBind – spice inside HDL simulator☆56Jun 30, 2025Updated 8 months ago
- ☆83Jan 5, 2026Updated 2 months ago
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆91Updated this week
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- The HW-CBMC and EBMC Model Checkers for Verilog☆103Updated this week
- SystemVerilog synthesis tool☆229Mar 10, 2025Updated 11 months ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆690Dec 26, 2025Updated 2 months ago
- Scheduling examples using C++20 coroutines☆29May 13, 2023Updated 2 years ago
- design and verification of asynchronous circuits☆43Feb 27, 2026Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆257Sep 30, 2025Updated 5 months ago
- Modular hardware build system☆1,131Updated this week
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆51Feb 19, 2026Updated 2 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languag…☆472Jan 18, 2026Updated last month
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- An open-source static random access memory (SRAM) compiler.☆1,016Jan 16, 2026Updated last month
- ☆15Dec 9, 2025Updated 2 months ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- A scalable High-Level Synthesis framework on MLIR☆290May 15, 2024Updated last year