dian-lun-lin / RTLflowLinks
A GPU acceleration flow for RTL simulation with batch stimulus
☆116Updated last year
Alternatives and similar repositories for RTLflow
Users that are interested in RTLflow are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆184Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated 2 weeks ago
- Next generation CGRA generator☆118Updated last week
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- ☆87Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆89Updated 7 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated last week
- A configurable SRAM generator☆56Updated 4 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆124Updated 2 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- ☆62Updated 2 weeks ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆43Updated 11 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆155Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago