merledu / caravanLinks
A caravan equipped with API for creating bus protocols in Chisel with ease.
☆14Updated 6 months ago
Alternatives and similar repositories for caravan
Users that are interested in caravan are comparing it to the libraries listed below
Sorting:
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆117Updated 2 weeks ago
- ☆166Updated 3 years ago
- ☆98Updated last year
- ☆57Updated 9 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆28Updated last month
- Python packages providing a library for Verification Stimulus and Coverage☆127Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- ☆99Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- Introductory course into static timing analysis (STA).☆98Updated 3 months ago
- UVM 1.2 port to Python☆253Updated 8 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Static Timing Analysis Full Course☆60Updated 2 years ago
- Control and status register code generator toolchain☆149Updated last week
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆74Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆64Updated 4 years ago
- ☆26Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆110Updated last year
- ☆208Updated 7 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 3 years ago
- ☆13Updated 3 years ago
- ☆15Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆105Updated last year
- ☆201Updated 7 months ago