merledu / caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
☆14Updated last month
Alternatives and similar repositories for caravan:
Users that are interested in caravan are comparing it to the libraries listed below
- Generic Register Interface (contains various adapters)☆113Updated 7 months ago
- ☆92Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆61Updated last year
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆74Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated last week
- Platform Level Interrupt Controller☆40Updated 11 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- Announcements related to Verilator☆39Updated 4 years ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆58Updated 3 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- RISC-V Verification Interface☆89Updated 2 months ago
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆102Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- Re-coded Xilinx primitives for Verilator use☆47Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 10 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- A Fast, Low-Overhead On-chip Network☆197Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆63Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- (System)Verilog to Chisel translator☆113Updated 2 years ago
- The multi-core cluster of a PULP system.☆89Updated 3 weeks ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago