merledu / caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
☆13Updated this week
Related projects ⓘ
Alternatives and complementary repositories for caravan
- Generic Register Interface (contains various adapters)☆100Updated last month
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- A SystemVerilog source file pickler.☆51Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆146Updated this week
- ☆75Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 6 months ago
- Announcements related to Verilator☆38Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆44Updated 4 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆108Updated this week
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- An Open-Source Design and Verification Environment for RISC-V☆76Updated 3 years ago
- A dynamic verification library for Chisel.☆142Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Open source high performance IEEE-754 floating unit☆60Updated 8 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 5 months ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆32Updated last month
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- Hardware generator debugger☆71Updated 9 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆23Updated this week
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago