awygle / waggle
Rust proof-of-concept for GPU waveform rendering
☆13Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for waggle
- Finding the bacteria in rotting FPGA designs.☆13Updated 3 years ago
- Industry standard I/O for nMigen☆13Updated 4 years ago
- ☆10Updated this week
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 4 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago
- ☆63Updated 4 years ago
- Smol 2-stage RISC-V processor in nMigen☆25Updated 3 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 2 years ago
- Wishbone bridge over SPI☆11Updated 4 years ago
- Cross compile FPGA tools☆22Updated 3 years ago
- Yet Another Debug Transport☆20Updated 2 years ago
- ☆10Updated 6 years ago
- Simplified environment for litex☆13Updated 4 years ago
- There are many RISC V projects on iCE40. This one is mine.☆13Updated 4 years ago
- 妖刀夢渡☆56Updated 5 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆32Updated 2 weeks ago
- My pergola FPGA projects☆30Updated 3 years ago
- Hot Reconfiguration Technology demo☆38Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆46Updated 10 months ago
- DDR3 controller for nMigen (WIP)☆14Updated 10 months ago
- cocotb extension for nMigen☆15Updated 2 years ago
- LiteX project for the ButterStick bootloader☆12Updated last year
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Industry standard I/O for Amaranth HDL☆26Updated 3 weeks ago
- USB virtual model in C++ for Verilog☆28Updated 3 weeks ago
- HDMI Expansion Modules compatible with the Pmod standard☆11Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- DVI video out example for prjtrellis☆16Updated 5 years ago
- A bit-serial CPU☆18Updated 5 years ago