parallella / parallella-riscvView external linksLinks
RISC-V port to Parallella Board
☆13Aug 22, 2016Updated 9 years ago
Alternatives and similar repositories for parallella-riscv
Users that are interested in parallella-riscv are comparing it to the libraries listed below
Sorting:
- ☆10Nov 8, 2019Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆107Nov 14, 2018Updated 7 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 5 months ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆15Nov 16, 2017Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Designs, infrastructure, and experiments around Race Logic☆25Jun 25, 2020Updated 5 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 4 years ago
- A template for building new projects/platforms using the BOOM core.☆25Jan 14, 2019Updated 7 years ago
- CNN accelerator☆29Jun 11, 2017Updated 8 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- ☆13May 11, 2016Updated 9 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆11Nov 8, 2020Updated 5 years ago
- Electrical and Computer Engineering Capstone☆10Jan 23, 2017Updated 9 years ago
- Medium Access Control layer of 802.15.4☆13Nov 14, 2014Updated 11 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- msfinance offers Pythonic way to download market data from morningstar.com☆15Feb 15, 2025Updated last year
- A simple IP address to geolocation service for use with the Google App Engine cloud platform.☆12May 17, 2015Updated 10 years ago
- Circuit Synthesis for Yao's Garbled Circuit by TinyGarble☆11Sep 25, 2020Updated 5 years ago
- Sia GPU miner☆10Jul 20, 2016Updated 9 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last week
- A Dependency Injection Container for node.js☆49Mar 28, 2015Updated 10 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- This SDK supports Box OneCloud integrations on Android that handle file ‘roundtrips’. That is, it enables file open-edit-save scenarios b…☆56Dec 10, 2014Updated 11 years ago
- A Python library used to transfer files with QR codes. Input a file, get QR code images. Print, email, or otherwise share your codes. Re-…☆10Sep 15, 2019Updated 6 years ago
- Post-Silicon Validation Tool based on REVERSI☆12Dec 10, 2025Updated 2 months ago
- PolarFire FPGA sample RISC-V designs☆14Oct 15, 2019Updated 6 years ago
- RTLMeter benchmark suite☆29Jan 25, 2026Updated 3 weeks ago
- functional template library☆15Jun 13, 2016Updated 9 years ago
- aggregate prefix to shorter list☆17Mar 22, 2024Updated last year
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12May 24, 2019Updated 6 years ago
- A normalizing interpreter for the untyped λ-calculus in 292 characters of Haskell☆10Mar 8, 2016Updated 9 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago