parallella / parallella-riscvLinks
RISC-V port to Parallella Board
☆13Updated 9 years ago
Alternatives and similar repositories for parallella-riscv
Users that are interested in parallella-riscv are comparing it to the libraries listed below
Sorting:
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆34Updated 10 years ago
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆146Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 10 months ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆87Updated 3 years ago
- A 32-bit RISC-V processor for mriscv project☆59Updated 8 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture☆64Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated last week
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago