parallella / parallella-riscvLinks
RISC-V port to Parallella Board
☆12Updated 9 years ago
Alternatives and similar repositories for parallella-riscv
Users that are interested in parallella-riscv are comparing it to the libraries listed below
Sorting:
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- firrtlator is a FIRRTL C++ library☆23Updated 8 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 weeks ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- RISC-V BSV Specification☆21Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 8 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆34Updated 10 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- RISC-V GPGPU☆34Updated 5 years ago
- OpenFPGA☆34Updated 7 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Libre Silicon Compiler☆22Updated 4 years ago
- BSC Development Workstation (BDW)☆30Updated 10 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 5 months ago
- ☆56Updated 3 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago