parallella / parallella-riscv
RISC-V port to Parallella Board
☆12Updated 8 years ago
Alternatives and similar repositories for parallella-riscv:
Users that are interested in parallella-riscv are comparing it to the libraries listed below
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆31Updated 9 years ago
- Open Processor Architecture☆26Updated 8 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 5 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 5 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 7 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Updated 4 years ago
- Useful utilities for BAR projects☆31Updated last year
- A Verilog Synthesis Regression Test☆35Updated 11 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- RISC-V GPGPU☆34Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- The BERI and CHERI processor and hardware platform☆47Updated 7 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- RISC-V BSV Specification☆18Updated 5 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 3 years ago
- ☆10Updated 5 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- Consistency checker for memory subsystem traces☆15Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- BSC Development Workstation (BDW)☆28Updated 3 months ago
- SPI core☆15Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week