x-epic / EpicFV
☆20Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for EpicFV
- Collection of test cases for Yosys☆17Updated 2 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- Mirror of tachyon-da cvc Verilog simulator☆37Updated last year
- Intel Compiler for SystemC☆23Updated last year
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 7 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- ☆39Updated 4 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆32Updated 9 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- A coverage library for Chisel designs☆11Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆31Updated last month
- ☆13Updated 3 years ago
- Benchmarks for Yosys development☆22Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆39Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- The home of the Chisel3 website☆20Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆17Updated 8 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week