x-epic / EpicFV
☆20Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for EpicFV
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- Intel Compiler for SystemC☆23Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- A coverage library for Chisel designs☆11Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆33Updated last year
- The PE for the second generation CGRA (garnet).☆16Updated 2 months ago
- ☆39Updated 4 years ago
- Handle Fast Signal Traces (fst) in Python☆10Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 7 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆28Updated this week
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 4 months ago
- Collection of test cases for Yosys☆16Updated 2 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- ☆13Updated 3 years ago
- ☆51Updated 2 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆21Updated 4 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆21Updated 8 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆18Updated last week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- ☆32Updated last year
- ☆18Updated 4 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆12Updated last month
- The multi-core cluster of a PULP system.☆56Updated last week
- Source codes and calibration scripts for clock tree synthesis☆39Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated 9 months ago
- Verilog behavioral description of various memories☆30Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago