Alternatives and similar repositories for protohdl

Users that are interested in protohdl are comparing it to the libraries listed below

• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆42Updated last month
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated 2 months ago
• olofk / observer
  ☆41Updated 5 years ago
• PyLCARS / PythonUberHDL
  Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
  ☆36Updated 6 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• Gekkio / docker-fpga
  Dockerized FPGA toolchain experiments
  ☆29Updated last year
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated 2 weeks ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated this week
• intel / multi_power_sequencer
  Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, s…
  ☆19Updated 3 months ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆55Updated last month
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated 3 weeks ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆44Updated 3 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 4 years ago
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆24Updated 3 years ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last month
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆94Updated 10 months ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆46Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆69Updated 7 years ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆80Updated 7 months ago
• psychogenic / microcotb
  micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop
  ☆15Updated 5 months ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆87Updated last year
• wavedrom / datasheet
  datasheet generator
  ☆28Updated 3 weeks ago