drom / icedromLinks
FPGA config visualized. demo:
☆19Updated 5 years ago
Alternatives and similar repositories for icedrom
Users that are interested in icedrom are comparing it to the libraries listed below
Sorting:
- FPGA Portable Music Generator☆11Updated 7 years ago
- Cross compile FPGA tools☆21Updated 4 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- OpenFPGA☆34Updated 7 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- iCE40 floorplan viewer☆24Updated 7 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- Yosys Plugins☆21Updated 6 years ago
- RISC-V processor☆31Updated 3 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Updated 4 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Small footprint and configurable HyperBus core☆13Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Open Processor Architecture☆26Updated 9 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆11Updated 6 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆29Updated 6 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 5 years ago