drom / icedromLinks
FPGA config visualized. demo:
☆19Updated 5 years ago
Alternatives and similar repositories for icedrom
Users that are interested in icedrom are comparing it to the libraries listed below
Sorting:
- Cross compile FPGA tools☆21Updated 4 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- FPGA Portable Music Generator☆11Updated 7 years ago
- OpenFPGA☆34Updated 7 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Generic Logic Interfacing Project☆47Updated 5 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆11Updated 7 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆61Updated 3 months ago
- PicoRV☆44Updated 5 years ago
- Yosys Plugins☆22Updated 6 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- A configurable USB 2.0 device core☆31Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated 2 weeks ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆10Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 3 months ago
- 妖刀夢渡☆60Updated 6 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago