Alternatives and similar repositories for hdl-secded-producer

Users that are interested in hdl-secded-producer are comparing it to the libraries listed below

• inferablejump / bagpype
  ☆15Updated 2 months ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• ucb-bar / chisel-awl
  ☆13Updated 4 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆34Updated last year
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆32Updated 11 months ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 6 months ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆25Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• nmi-leipzig / sim-x-pll
  Verilog based simulation modell for 7 Series PLL
  ☆17Updated 5 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆21Updated last month
• abs-tudelft / Tydi-Chisel
  ☆18Updated 3 weeks ago
• chipsalliance / rocket
  The working draft to split rocket core out from rocket chip
  ☆14Updated last year
• TsaiAnson / verif
  ☆12Updated 4 years ago
• jjyy-Huang / SpinalHDL-ethernet
  ☆20Updated 2 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆18Updated 3 years ago
• ucb-art / fft
  ☆20Updated 5 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• easysoc / layered-firrtl
  This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl
  ☆11Updated 3 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago
• sequencer / arithmetic
  ☆33Updated 7 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆31Updated 2 months ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆15Updated 6 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆30Updated 9 months ago
• Dinistro / circt-stream
  A stream to RTL compiler based on MLIR and CIRCT
  ☆15Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆66Updated 11 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆49Updated 2 weeks ago