iDoka / hdl-secded-producer

Related projects ⓘ

Alternatives and complementary repositories for hdl-secded-producer

• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 4 years ago
• chipsalliance / rocket
  The working draft to split rocket core out from rocket chip
  ☆14Updated 10 months ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆11Updated 5 years ago
• ucb-art / fft
  ☆19Updated 4 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• uenoku / firtool-standalone-plugin
  an experiment to run plugin in firtool pipeline
  ☆9Updated last year
• ucb-bar / chisel-awl
  ☆13Updated 3 years ago
• pulp-platform / axi_llc
  ☆20Updated 2 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆10Updated 3 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 2 years ago
• TsaiAnson / verif
  ☆11Updated 3 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆30Updated this week
• mattvenn / logo-to-gds2
  ☆16Updated last year
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 4 months ago
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆13Updated 5 years ago
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆13Updated last year
• jjyy-Huang / SpinalHDL-ethernet
  ☆15Updated last year
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 2 years ago
• ucb-art / craft2-chip
  Craft 2 top-level repository
  ☆13Updated 5 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆27Updated 10 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆23Updated 4 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆16Updated last month
• IObundle / iob-mem
  Verilog behavioral description of various memories
  ☆30Updated 2 years ago
• sequencer / arithmetic
  ☆31Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated this week
• easysoc / layered-firrtl
  This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl
  ☆11Updated 3 years ago