Alternatives and similar repositories for la-core

Users that are interested in la-core are comparing it to the libraries listed below

• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated this week
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆76Updated 6 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆55Updated 5 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 11 years ago
• falconcomputing / merlin-compiler
  Falcon Merlin Compiler
  ☆41Updated 5 years ago
• lana555 / dynamatic
  ☆87Updated last year
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆171Updated 2 weeks ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 10 months ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 3 years ago
• CMU-SAFARI / NOCulator
  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…
  ☆29Updated 2 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated last week
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last week
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• pulp-platform / redmule
  ☆90Updated 3 weeks ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆116Updated 3 weeks ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆73Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆69Updated 6 years ago