Alternatives and similar repositories for la-core:

Users that are interested in la-core are comparing it to the libraries listed below

• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆110Updated this week
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆85Updated 2 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆69Updated 5 years ago
• lana555 / dynamatic
  ☆86Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆81Updated 5 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆41Updated 2 weeks ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆120Updated 5 years ago
• arcade-lab / tia-infrastructure
  ☆18Updated 7 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 5 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆45Updated 2 weeks ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated last month
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆56Updated 5 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆35Updated 3 years ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆35Updated 8 years ago
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆49Updated 6 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago