Alternatives and similar repositories for la-core

Users that are interested in la-core are comparing it to the libraries listed below

• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆116Updated last week
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 2 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 6 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 11 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated 2 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆126Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• pulp-platform / redmule
  ☆88Updated this week
• falconcomputing / merlin-compiler
  Falcon Merlin Compiler
  ☆41Updated 5 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆82Updated 9 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆167Updated last month
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆111Updated this week
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• StanfordAHA / aha
  ☆61Updated this week
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• lana555 / dynamatic
  ☆87Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 8 months ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 5 years ago
• CMU-SAFARI / NOCulator
  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…
  ☆27Updated 2 years ago
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆65Updated 6 years ago
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 4 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆43Updated 5 months ago