Alternatives and similar repositories for la-core:

Users that are interested in la-core are comparing it to the libraries listed below

• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆51Updated 5 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆86Updated 2 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆41Updated last month
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆69Updated 5 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆40Updated last week
• PrincetonUniversity / accelerator-wall
  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.
  ☆49Updated 6 years ago
• lana555 / dynamatic
  ☆86Updated last year
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 9 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 6 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆40Updated last year
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆57Updated 5 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆45Updated last month
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆120Updated 10 months ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• StanfordAHA / aha
  ☆57Updated this week
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated 2 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆164Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• arcade-lab / tia-infrastructure
  ☆18Updated 7 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆38Updated 7 months ago