An example OMI Device FPGA with 2 DDR4 memory ports
☆20Jan 5, 2023Updated 3 years ago
Alternatives and similar repositories for omi_device_ice
Users that are interested in omi_device_ice are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tenstorrent Blackhole P100/P150 card RISC-V Linux demo 🐧☆46Updated this week
- 360nosc0pe Yocto build environment☆12Aug 27, 2018Updated 7 years ago
- PowerPC FSI Debugger☆18Updated this week
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆24Oct 15, 2025Updated 5 months ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆15Mar 26, 2026Updated 2 weeks ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Free open source EDA tools☆66Oct 1, 2019Updated 6 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Jun 25, 2020Updated 5 years ago
- VexRiscv-SMP integration test with LiteX.☆25Nov 16, 2020Updated 5 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- LiteX LUNA USB stack integration☆14Jun 12, 2022Updated 3 years ago
- Witches Town extended extended informations☆12Apr 1, 2018Updated 8 years ago
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆15Oct 24, 2019Updated 6 years ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- ☆15Oct 2, 2023Updated 2 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- ☆13May 28, 2022Updated 3 years ago
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 9 months ago
- HDL components to build a customized Wishbone crossbar switch☆14May 30, 2019Updated 6 years ago
- ☆30Aug 19, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A tiny POWER Open ISA soft processor written in Chisel☆114Feb 13, 2023Updated 3 years ago
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- ☆16Apr 21, 2022Updated 3 years ago
- Binary Decompilation of the Polo G40 Digifant-1 Controller☆11Oct 21, 2018Updated 7 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Firmware and Gateware for the DiVA platform.☆14Sep 8, 2025Updated 7 months ago
- ☆30Dec 11, 2025Updated 3 months ago