Alternatives and similar repositories for ligeia:

Users that are interested in ligeia are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆88Updated 6 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• pieter3d / simview
  ☆78Updated last year
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆82Updated last month
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆142Updated last year
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• olofk / corescore
  CoreScore
  ☆151Updated 3 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 2 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆44Updated 4 months ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆33Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 6 months ago
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆139Updated 2 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆114Updated last month
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆76Updated 3 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆67Updated 3 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆108Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated last week
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago