Alternatives and similar repositories for ligeia

Users that are interested in ligeia are comparing it to the libraries listed below

• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last year
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆94Updated 2 months ago
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆143Updated 10 months ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆145Updated last week
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆49Updated last year
• olofk / corescore
  CoreScore
  ☆171Updated 2 months ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆102Updated 2 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆42Updated 3 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆31Updated last year
• djg / verilated-rs
  Verilator Porcelain
  ☆49Updated 2 years ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆24Updated 3 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated last year
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆81Updated 2 weeks ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆105Updated last week
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated last week
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆122Updated 5 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆74Updated 4 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆253Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆27Updated 3 years ago
• regymm / GenZ
  The open-source Zynq 7000 BSP generator for openXC7
  ☆51Updated last year
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• Ravenslofty / blog
  The Critical Path - a rambly FPGA blog
  ☆51Updated 5 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 4 years ago
• pieter3d / simview
  ☆89Updated 3 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆82Updated 3 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆90Updated 2 weeks ago